double gate mosfet, dgt

1. DOUBLE - GATE MOSFET
BY,
A. POOJA SHUKLA
1821310006
M. Tech ( I Yr )
SRM UNIVERSITY

2. A BASIC MOSFET:

3. MOSFET Transistor Fabrication Steps

4. MOSFET OPERATION
Step 1: Apply Gate Voltage
SiO2 Insulator (Glass)
Gate
Source
Drain
5 volts
holes
N
N
electrons
P
electrons to be
transmitted
Step 2: Excess electrons surface
in channel, holes are repelled.
Step 3: Channel becomes
saturated with electrons.
Electrons in source are able to
flow across channel to Drain.

5. Scaling limits of BULK MOSFET
 Limit
for supply voltage (<0.6V)
 Limit
for further scaling of tox (<2nm)
 Minimum
 Discrete
channel length Lg=50nm
dopant fluctuations
 Dramatic
short-channels effects (SCE)

6. Problem 1: Carrier Mobility Decreases as Channel
length decrease and Vertical Electric fields increase
Problem 2: VT Rolloff as Channel length decreases
Problem 3: Tunneling Through Gate Oxide (off state
current)
Problem 4: Wattage/Area increases as density increases

7. How can we follow Moore’s law ?
 By moving to DG MOSFETs
DG might be the unique viable alternative to build nano
MOSFETs when Lg<50nm
Because:
- Better control of the channel from the gates
- Reduced short-channel effects
- Better Ion/Ioff
- Improved sub-threshold slope (60mV/decade)
- No discrete dopant fluctuations

8. Double Gate MOSFET
Features:
• Upper and lower gates control the channel region
• Ultra-thin body acts as a rectangular quantum well at device limits
• Directly scalable down to 20 nm channel length

9. Silicon-on-Insulator (SOI) Approach
 Silicon channel layer grown on a layer
of oxide.
 Absence of junction capacitance makes
this an attractive option.
 Low leakage currents and compatible
fabrication technology.

10. Silicon-on-Insulator (SOI) Approach
 Silicon channel layer grown on a layer
of oxide.
 Absence of junction capacitance makes
this an attractive option.
 Low leakage currents and compatible
fabrication technology.

12. To reduce SCE’s,
aggressively
reduce Si layer
thickness
E-Field lines
G
S
BOX
Double gates
electrically shield
the channel
G
D
S
BOX
D
G
Double-Gate
Regular SOI MOSFET Double-gate MOSFET
Single-Gate SOI

13. Gate
n+ poly gate
Gate
Vdd
n+ source
n+ drain
Vdd
n+
source
n+
drain
p substrate
Gate
• Single Gate to Double Gates
–Better short-channel effect control
–More Scalable

14. •
•
•
•
Higher current drive
better performance
Prophesized to show higher tolerance to scaling.
Better integration feasibility, raised source-drain structure, ease in integration.
Larger number of parameters to tailor device performance

15. Layout
• Type I : Planar Double Gate
• Type II: Vertical Double Gate
• Type III: Horizontal Double Gate (FinFET)

16. Reduced Channel and Gate Leakage
• Short channel effects are seen in Standard silicon MOS devices
• DGFET offers greater control of the channel because of the double gate
• Gate leakage current is prevented by a thick gate oxide

17. Threshold Voltage Control
Silicon MOS Transistor:
• Increased body doping used to control VT for short channel
• Small number of dopant atoms for very short channel
• Lowest VT achievable is .5V
Double Gate FET :
• Increased body doping
• Asymmetric gate work functions (n+ / p+ gates)
• Metal gate
• VT of .1V achievable through work function engineering

18. Increased Carrier Mobility
Silicon MOS Transistor:
• Carrier scattering from increased body doping
• Transverse electric fields from the source and drain reduce mobility
Double Gate FET:
• Lightly doped channel in a DGFET results in a negligible depletion charge
• Asymmetric gate: experiences some transverse electric fields
• Metal gate: transverse electric field negligible with increased channel control

19. Reduced Power Consumption
• Double Gate coupling allows for higher drive currents at lower supply
voltage and threshold voltage
• Energy is a quadratic function of supply voltage
• Reduced channel and gate leakage currents in off state translate to huge
power savings
• Separate control of each gate allows dynamic control of VT :
Simplified logic gates would save power and chip area

20. Challenges Facing Double Gate Technology
1) Identically sized gates
2) Self-alignment of source and drain to both gates
3) Alignment of both gates to each other
4) Connecting two gates with a low-resistance path

21. Ultimate Double Gate Limits
1) Thermionic emission above the channel potential barrier:
Short channel effects lower potential barrier
2) Band-to-band tunneling between body and drain pn junction:
Body-drain electric field increases tunneling probability
3) Quantum mechanical tunneling directly between source and drain:
Extremely small channel lengths correspond to narrow
potential barrier width
4) Other effects of quantum confinement in the thin body

22. Front Gate
• Short channel effect control
– Better scalability
– Lower sub threshold
current
• Higher On Current
• Near-Ideal Sub threshold
slope
• Lower Gate Leakage
• Elimination of Vt variation
due to Random dopant
fluctuation
Gate
(metal/poly)
Source
n+
source
body
Drain
n+
drain
Gate
(metal/poly)
Back Gate
DG devices are very
promising for circuit
design in sub-50nm
technology

23. THANK YOU…….!!!