Learn about the new 28-nm Stratix V FPGA family from Altera. Built for bandwidth, this family includes 28-Gbps transceivers, embedded HardCopy blocks, and variable-precision DSP blocks.

1. Stratix V FPGAs: Built for Bandwidth April 2010

7. Stratix V Device Family Plan Note: Subject to change. See the Stratix V handbook for the latest information. Device Interconnect Hard IP Core Fabric Transceivers (12.5G, 28G) GPIO 72-Bit DDR3 x8 PCIe Gen3 40G/100G Ethernet LEs Memory (Mb) 18x18 Multipliers fPLLs Stratix V GT FPGA 5SGT B5 32, 4 597 4 1 Yes 424K 47 640 32 5SGT B7 32, 4 597 4 1 Yes 635K 51 684 32 Stratix V GX FPGA 5SGX A3 36, 0 624 4 1 or 2 Yes 239K 29 400 24 5SGX A4 36, 0 624 4 1 or 2 Yes 311K 33 486 24 5SGX A5 48, 0 840 6 1 or 4 Yes 424K 47 640 32 5SGX A7 48, 0 840 6 1 or 4 Yes 635K 51 684 32 5SGX B5 66, 0 648 4 1 or 4 Yes 403K 41 700 32 5SGX B6 66, 0 648 4 1 or 4 Yes 536K 53 738 32 Stratix V GS FPGA 5SGS B5 27, 0 1,020 7 1 or 2 No 482K 32 3,310 16 5SGS B7 27, 0 1,020 7 1 or 2 No 726K 40 3,680 16 Stratix V E FPGA 5SE B9 - 900 7 - No 968K 33 1,064 32 5SE BA - 900 7 - No 1,087K 43 1,100 32

8. Stratix V Device Package Plan Notes: Flip-chip ball-grid array (BGA) with 1.0-mm pitch GPIO, LVDS, transceivers Pin migration Note: Subject to change. See the Stratix V handbook for the latest information. Device F780 (29 mm) F1152 (35 mm) F1152 (35 mm) F1517 (40 mm) F1517 (40 mm) F1932 (45 mm) 5SGT B5 597, 149, 36 5SGT B7 597, 149, 36 5SGX A3 270, 68, 24 560, 140, 24 444, 111, 36 624, 156, 36 5SGX A4 270, 68, 24 560, 140, 24 444, 111, 36 624, 156, 36 5SGX A5 560, 140, 24 444, 111, 36 707, 176, 36 597, 149, 48 840, 210, 48 5SGX A7 560, 140, 24 444, 111, 36 707, 176, 36 597, 149, 48 840, 210, 48 5SGX B5 439, 109, 66 648, 162, 66 5SGX B6 439, 109, 66 648, 162, 66 5SGS B5 523, 130, 27 781, 195, 27 1020,255,27 5SGS B7 523, 130, 27 781, 195, 27 1020,255,27

9. Stratix V Hard IP Variants Stratix V FPGA: PCI Express Stratix V FPGA: 40G/100G PCIe Gen3 Mainstream variant with one hard IP for PCI Express Gen3, Gen2, and Gen1 x8 Stratix V FPGA: Mainstream 40G/100G variant with hard PCS IP for 40G/100G Ethernet and one hard IP for PCI Express Gen3, Gen2, and Gen1 x8 All Hard IP Variants Support Configuration via PCI Express (CvPCIe) PCI Express enhanced variant with up to 4 hard IP instances for PCI Express Gen3, Gen2, and Gen1 x8 PCIe Gen3 PCIe Gen3 PCIe Gen3 PCIe Gen3 PCIe Gen3 40G/100G 40G/100G 40G/100G

10. Stratix V Transceiver, Memory, and I/O Innovations Built for Bandwidth

16. 10G Protocols Supported in Stratix V FPGAs New or enhanced in Stratix V FPGAs Note: Subject to change. See the Stratix V handbook for the latest information. Standard Electrical Serial Line Rate Link Lanes HIP 10G IEEE 802.3ba 40G 10.3125 Gbps Chip-to-module and BP 4 Yes IEEE 802.3ba 100G 10.3125 Gbps Chip-to-module 10 Yes IEEE 802.3ae 10GBASE-R 10.3125 Gbps Chip-to-module 1 to N Yes IEEE 802.3ba 10GBASE-KR 10.3125 Gbps Backplane 1 to N Yes 10G GPON/EPON 10 Gbps C2C and C2M 1 to N Yes OIF SFI-S 9.95 to 11.1 Gbps Chip-to-module (8,10, 12, 16) +1 OIF SFI-5.2 (40G) 9.95 to 11.1 Gbps Chip-to-module 5 10G Interlaken 10.6921 Gbps Chip-to-chip, cable 1 to N Yes SONET/SDH OC-192 (10G) 9.95 Gbps Chip-to-chip 1 to N SONET/SDH OC-192 (40G) 9.95 Gbps Chip-to-chip 4 SFP+ 8.5 to 11.32 Gbps Optical module std 1 to N Yes XFP 9.95328 to 11/32 Gbps Optical module std 1 to N OIF/CEI 11G-SR 9.95 to 11.1 Gbps Chip-to-chip I/O technology OIF/CEI 11G-LR 9.95 to 11.1 Gbps Backplane I/O technology OTU-2 10.709 Gbps Chip-to-chip See SFI-S OTU-3 10.7545 Gbps SFI-S See SFI-S OTU-4 11.2 Gbps SFI-S See SFI-S 10G SDI 10.6921 Gbps Chip-to-chip, cable 1 to N QDR InfiniBand 10 Gbps Chip-to-module 1 to N

17. 6G Protocols Supported in Stratix V FPGAs New or enhanced in Stratix V FPGAs Note: Subject to change. See the Stratix V handbook for the latest information. Standard Electrical serial line rate Link Lanes HIP 6G PCIe 3.0 8 Gbps Chip-to-module and BP 1, 2, 4, 8 Yes PCIe 2.0 5 Gbps Chip-to-module and BP 1, 2, 4, 8 Yes Interlaken 4.976 Gbps to 6.375 Gbps Chip-to-module and BP 1 to 24 Yes SRIO 2.0+ 1.25, 2.5, 3.125, 5 to 6.25 Gbps Chip-to-module and BP 1, 2, 4 Yes CPRI 4.0+ 0.6144, 1.2288, 2.4576, 3.072, 4.9152, 6.144 Gbps Chip-to-chip 1 to N Yes OBSAI 4.0+ (RP3) 0.768, 1.536, 3.072, 6.144 Gbps Chip-to-module and BP 1 to N SATA 3.0 6 Gbps Chip-to-module and BP 1 to N SAS 2.0 6 Gbps Chip-to-module and BP 1 to N SPAUI 6.375 Gbps Chip-to-chip and BP 4 or 6 DDR-XAUI 6.25 Gbps Chip-to-chip and BP 4 QPI 4, 4,8, 6.4, 8 Gbps Chip-to-chip (5, 10, 20)+1 HyperTransport™ 3.0+ 0.4, 2.4, 2.8, 3.2 Gbps Chip-to-module and BP (2, 4, 8)+2, (16)+4 HighGig+, HighGig2+ 3.75, 6.25 Gbps Chip-to-module and BP 4 8G FC 8.5 Gbps C2C and C2M 1 to N OIF/CEI 6G-SR 4.976 to 6.375 Gbps Chip-to-chip I/O technology OIF/CEI 6G-LR 4.976 to 6.375 Gbps Backplane I/O technology 4G FC 4.25 Gbps C2C and C2M 1 to N

18. 3G Protocols Supported in Stratix V FPGAs New or enhanced in Stratix V FPGAs Note: Subject to change. See the Stratix V handbook for the latest information. Standard Electrical Serial Line Rate Link Lanes HIP 3G GIGE (Cisco SGMII) 1.25 Gbps Chip-to-chip 1 to N GIGE (IEEE 1000 Base-X) 1.25 Gbps C2C and C2M 1 to N SD-SDI/HD-SDI/3G-SDI 0.270, 1.485, 2.970 Gbps Chip-to-chip, cable 1 to N SATA 1.0/2.0 1.5 and 3 Gbps Chip-to-chip and BP 1 to N SAS 1.0 3 Gbps Chip-to-chip and BP 1 to N SRIO 1.0 (1.3) 1.25, 2.5, 3.125, 5 Gbps Chip-to-chip and BP 1, 4 Yes JESD204A 3.125 Gbps Chip-to-chip 1 to 32 XAUI 3.125 Gbps Backplane 4 Yes PCIe 1.0 2.5 Gbps Chip-to-chip and BP 1, 2, 4, 8 Yes GPON 0.155, 0.622, 1.244, 2.488 Gbps Chip-to-chip 1 to N CPRI 2.0+ 0.6144, 1.2288, 2.4576 Gbps Chip-to-chip 1 to N OBSAI 4.0 (RP3) 0.768, 1.536, 3.072 Gbps Chip-to-chip and BP 1 to N SONET/SDH OC-12, OC-48 0.622 to 2.488 Gbps Chip-to-chip 1 to N SFI-4.2 (10G) 3.125 Gbps Chip-to-chip 4 SFI-5.1 (40G) 3.125 Gbps Chip-to-chip 16 TFI-5 (40G) 2.488 to 3.11 Gbps Chip-to-chip 16 Sxl-5 2.488 to 3.125 Gbps Chip-to-chip I/O technology SPI-4.2 (10G) 0.622 Gbps Chip-to-chip 16 SPI-5.1 (40G) 2.5 Gbps Chip-to-chip 16

21. Stratix V Hard IP

23. Stratix V Integrated Hard IP More Available Logic for Higher System Integration in a Smaller FPGA Embedded HardCopy Block Hard IP PCIe Gen3, Gen2, Gen1 x8 PCS, PHY/MAC, data link, transaction layer 40GE/100GE MLD/PCS – gearbox, block sync, alignment marker, reorder virtual channel, async buffer/deskew, block striper/destriper, scrambler/descrambler Transceiver PCS Hard IP Interlaken Gearbox, block sync, 64b/67b, frame sync, scrambler/descrambler, CRC-32, async buffer/deskew 10GE (10GBASE-R) Gearbox, block sync, scrambler/descrambler, 64b/66b, rate matcher Serial RapidIO ® 2.0 Word aligner, lane sync state machine, deskew, rate matcher CPRI/OBSAI Word aligner, bit slip (deterministic latency)

24. Higher Effective Density With Stratix V Hard IP Stratix V FPGA 5SGXA7 ~630K LEs PCIe Gen3 x8 PCIe Gen3 x8 12 Ch @ 5G Interlaken 12 Ch @ 5G Interlaken Integrated Hard IP Enables a 630K-LE Stratix V FPGA to Be Equivalent to a 1070K-LE Part 630K LEs + 440K LEs = 1,070K LEs Interlaken – PCI Express Switch/Bridge Higher Effective Density Hard IP LE Savings Interlaken (24 Ch @ 5K LEs) 120K LEs PCIe Gen3 x8 (2 x 160K LEs) 320K LEs Total LE savings 440K LEs

25. Stratix V FPGA Core Innovations

30. Variable DSP Block Configurations Independent Multipliers 9 x 9 Three per block 18 x 18 with 32-bit resolution Two per block 27 x 27 One per block 18 x 36 One per block 36 x 36 Two cascaded blocks 54 x 54 Four cascaded blocks Independent Complex multipliers 18 x 25 Three cascaded blocks 27 x 27 Four cascaded blocks Sum of Multipliers Two 18 x 18 One per block Four 18 x 18 Two cascaded blocks Two 18 x 36 Two cascaded blocks Two 27 x 27 Two cascaded blocks

36. Innovations and Techniques to Control Power At the Industry’s Highest Performance, Stratix V FPGAs Deliver 30% Less Core Power Power Reduction Method Lower Static Power Lower Dynamic Power 28-nm Process Innovations   Programmable Power Technology  Lower Core Voltage (0.85 V)   Extensive Hardening of IP, Embedded HardCopy Blocks   Hard Power-Down of Functional Blocks   Clock Gating  Customized Extra-Low Leakage Devices  Partial Reconfiguration   DDR3 and Dynamic On-Chip Termination  

39. Stratix V FPGA IP, Reference Designs, and Development Kits

41. Altera’s IP Portfolio Highlights for Stratix V FPGAs Function Solution Type Provider Hard 10/40/100 Gbps Ethernet PCS IP core (hard) Altera Soft 40/100 Gbps Ethernet MAC and PCS IP core Altera and partner 10GBASE-R PCS IP core (hard) Altera 10G Ethernet MAC IP core Altera and partner Gigabit Ethernet MAC and PCS IP core Altera XAUI PCS IP core (hard) Altera Hard PCI Express Gen3, Gen2, Gen1 IP core (hard) Altera Soft PCI Express Gen3, Gen2, Gen1 IP core Altera and partner Interlaken (Hard PCS) IP core Altera Serial RapidIO Gen2 IP core Altera SFI 4.1, 5.1, 5.2 and SFI-S IP core Partner CPRI IP core Altera DDR1/2/3 SDRAM IP core Altera QDR II/QDR II + SRAM IP core Altera RLDRAM II IP core Altera and partner Floating-Point DSP Functions IP core Altera

42. Reference Designs and Development Kits Reference Designs Function Solution Type Provider 100G Aggregation to Interlaken Reference design Altera Deep Packet Inspection Reference design Partner High-Assurance Security Supervisor Reference design Partner Ethernet to Optical Transfer for OTN4 Reference design Partner Partial Reconfiguration for OTN4 Muxponder Reference design Altera and partner 40G Packet Processing and Traffic Management Reference design Altera 100G MAC-Interlaken Bridge Reference design Altera and partner HyperTransport™ 3.0 Reference design Partner PCI Express Gen3, Gen2, Gen1 Reference design Altera DDR1/2/3 SDRAM Reference design Altera Development Kits Function Provider Function FPGA Development Kit Altera FPGA Development Kit Signal Integrity and Interoperability Kit Altera Signal Integrity and Interoperability Kit Packet Datapath Processing Altera Packet Datapath Processing OTN4 With Ethernet Optical to Transport Partner OTN4 With Ethernet Optical to Transport