its a brief description about power consumption in circuit and reduction techniques.

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An assignment on
LOW POWER VLSI DESIGN
(EEC7208)
POWER CONSUMPTION IN CIRCUIT
By
Anil Kumar Yadav
Reg. no.: 13304025
(M.Tech electronics)
Department Of Electronics Engineering
School Of Engineering and Technology
Pondicherry University

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Table of content
Content
Page no.
1. Introduction
1.1 Is Power Really A Problem?
1.2 Do We Need To Bother With Power?
1.3 Why Power Matters in SOC?
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2. Sources of power consumption in digital CMOS circuits
2.1 Short-circuit power
2.2 Leakage power
2.3 Static Power
2.4 Switching power
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3. Low-Power Design Techniques 7
4. Power reduction techniques at circuit level:
4.1 Transistor and Gate Sizing of an Inverter
4.2 Chain Equivalent Pin Ordering
4.3 Network Restructuring and Reorganization
4.4 Transistor Network Partitioning and Reorganization
4.5 Flip Flops & Latches design
4.6 Self-gating Flip-flop
4.7 Combinational flip flop
4.8 Double Edge Triggered flip flop
4.9 Low Power Digital Cell Library
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5.CONCLUSION 17
6.REFERENCES 18

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Abstract.
In designing digital circuits and systems, minimizing power consumption has gained
considerably insignicance compared to the traditional cost metrics of silicon area, performance
and testability. The increasing importance of low power consumption is due to the ever
decreasing feature sizes of microelectronic circuits, higher clock frequencies and larger die sizes,
as well as the growing number of mobile, battery-operated systems.
To contain power optimization, modern design methodologies therefore allow optimizing power
on all levels during the design flow, from system level down to technology level. These
optimizations are either applied manually by the design engineer or automatically using CAD
tools.
This report gives an overview of the state-of-the-art in minimizing power consumption at circuit
levels of the design of digital circuits and systems.

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1. Introduction
During the desktop PC design era VLSI design efforts have focused primarily on optimizing
speed to realize computationally intensive real-time functions such as video compression,
gaming, graphics etc. As a result, we have semiconductor ICs that successfully integrated various
complex signal processing modules and graphical processing units to meet our computation and
entertainment demands , which need to pack all this without consuming much power. The strict
limitation on power dissipation in portable electronics applications such as smart phones and
tablet computers must be met by the VLSI chip designer while still meeting the computational
requirements. Reducing the total power consumption in such systems is important since it is
desirable to maximize the run time with minimum requirements on size, battery life and weight
allocated to batteries. So the most important factor to cosider while designing SoC for portable
devices is 'low power design'.
1.1 Is Power Really A Problem?
Scaling of technology node increases power-density more than expected. CMOS technology
beyond 65nm node represents a real challenge for any sort of voltage and frequency scaling
Starting from 120nm node, each new process has inherently higher dynamic and leakage current
density with minimal improvement in speed. Between 90nm to 65nm the dynamic power
dissipation is almost same whereas there is ~5% higher leakage/mm2.Low cost always continues
to drive higher levels of integration, whereas low cost technological breakthroughs to keep
power under control are getting very scarce. Modern System-on-Chip demand for more power.
In both logic and memory, Static power is growing really fast and Dynamic power kind of
grows. Overall power is dramatically increasing. If the semiconductor integration continue to
follow Moore's Law, the power density inside the chips will reach far higher than the rocket
nozzle.
1.2 Do We Need To Bother With Power?
Power dissipation is the main constrain when it comes to Portability. The mobile device
consumer demands more features and extended battery life at a lower cost. About 70% of users
demand longer talk and stand-by time as primary mobile phone feature. Top 3G requirement for
operators is power efficiency. Customers want smaller & sleeker mobile devices. This requires
high levels of Silicon integration in advanced processes, but advanced processes have inherently
higher leakage current. So there is a need to bother more on reducing leakage curret to reduce
power consumption.
1.3 Why Power Matters in SOC?
Power Management matter in System on Chip due to following concerns
a)Packaging and Cooling costs.
b)Digital noise immunity,
c)Battery life (in portable systems)
d)Environmental concerns.

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2. Sources of power consumption in digital CMOS circuits:
There are four components which contribute to the average power consumption Pavg of a digital
CMOS circuit:
Pavg = Pleakage + Psc + Pswitching + Pstatic;
Where Switching power P = CV2
fα
Short circuit power P = IscV
Leakage power P = IleakageV
Static power P = IstaticV
α : switching activity factor
2.1 Leakage power
Leakage power is caused by substrate injection at p/n junctions and subthreshold effects which
are primarily determined by fabrication technology. It contributes less than 1% to the average
power consumption and can therefore be ignored for our purposes. It is, however, important in
the context of ultra low-power systems with a very small VDD, as used in microelectronic
systems for medical applications.
The PMOS and NMOS transistors used in a CMOS logic circuit commonly have non-zero
reverse leakage and sub-threshold currents. These currents can contribute to the total power
dissipation even when the transistors are not performing any switching action. The leakage
power dissipation, P leakage is caused by two types of leakage currents.
The leakage power dissipation, P leakage is caused by two types of leakage currents
a) Reverse-bias diode leakage current
b) Sub threshold current through a turned-off transistor channel
2.2 Short-circuit power
Short-circuit power is caused by currents which temporarily occur when both the n- and p-parts
of a gate are open while the gate is switching.
Suppose the input X to the CMOS inverter in Figure 2 is making a transition from logic '0' to
logic '1'. While the p-device is being turned OFF and the n-device is being turned ON, there is
a short period of time during which there is a direct current path from VDD to ground. This
current is called the short-circuit current Isc. It typically accounts for 10% to 20% of the overall
power consumption.

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The short-circuit dissipation of the gate varies with the output load and the input signal
slope. The short-circuit dissipation decreases linearly (roughly) in both absolute terms
and a fraction of the total dissipation as the output load is increased to a critical value and
then it will increase again rapidly .
For simplicity a symmetrical inverter (i.e., βN = βp and VTn = -Vtp;) and a symmetrical
input signal (rise time = fall time) are considered.
I = β/2(Vin – V T)2
for 0≦ I≦ Imax
Imean = 1/T ∫0
T
I(t) dt = 2* 2/T ∫t1
t2
β/2 (Vin (t) – VT)2
dt
Assuming the rising and falling portions of the input voltage waveform to be linear
ramps,
Vin(t) = t* VDD/τ
Imean = 2*2/T∫(Vt/Vdd) τ
τ/2
β/2(t*VT/τ – VT)2
dt
Let θ= (VT/τ)t - VT
Imean = - 2β/T∫(Vt/Vdd) τ
τ/2
θ dθ
Imean = 1/12*β/VDD(VDD – VT)3
τ/T
The short-circuit power dissipation of an unloaded inverter is
PSC = β/12(VDD – VT)3
τ/T
If the inverter is lightly loaded, causing output rise and fall times that are relatively
shorter than the input rise and fall times, the short-circuit dissipation increases to become
comparable to dynamic dissipation
To minimize dissipation, an inverter should be designed in such a way so that the input
rise and fall times are about equal to the output rise and fall times.
2.3 Static Power
Static power is the power dissipated by a gate when it is not switching that is, when it is
inactive or static. Ideally, CMOS (Complementary Metal Oxide Semiconductor) circuits
dissipate no static (DC) power since in the steady state there is no direct path from Vdd to
ground. This scenario can never be realized in practice, since in reality the MOS
transistor is not a perfect switch. There will always be leakage currents, sub threshold
currents, and substrate injection currents, which give rise to the static component of
power dissipation. The largest percentage of static power results from source-to-drain sub
threshold voltage, which is caused by reduced threshold voltages that prevent the gate
from completely turning off.
2.4 Switching power
The switching power, also called dynamic or capacitive power, is by far the most signi_cant
component and accounts for approximately 80% of the overall power consumption. Switching
power is dissipated when the capacitive load C(y) of a CMOS gate is being charged by the
current Iswitch through the p-device to make a transition from ground to VDD. The energy
required for this transition is C(y)V2
DD. Power-consuming transitions occur at a frequency

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1/2𝛼(y)fclk proportional to the clock frequency fclk, where 𝛼(y) is the probability of signal y to
make a '0' to '1' or '1' to'0' transition.
The total switching power of a circuit is therefore:
above Eq. shows that the switching power increases linearly with the clock frequency. To
reduce the switching power even for increasing clock frequency, we therefore have the following
opportunities:
Since the supply voltage VDD influences the Pswitching quadratically, it is most effective to
reduce VDD. However, a lower supply voltage also results in slower switching speed and
therefore degrades performance of the circuit accordingly. The relationship between delay, i.e.
clock frequency, can be expressed as follows:
where Vt is the threshold voltage of the given technology.
To reduce the switched capacitance Psignal y _(y)C(y) of the circuit, we can decrease the
switching activity of a signal y by appropriately restructuring and/or modifying the fanin logic
feeding signal y. Alternatively, we can reduce the actual physical capacitance C(y) to be
switched by a signal y. C(y) depends on the output capacitance of the corresponding gate, the
wiring capacitance and the gate capacitances of the fanout gates. All of these are in turn
dependent on the technology used. However, it is important to note that wiring length does not
scale proportionally to the feature sizes of the underlying technology, but that its scaling
behavior depends on the wire locality. For global wires, capacitance typically grows with
technology scaling. Therefore, global wiring capacitance is becoming a dominating parameter in
C(y) for deep-submicron technologies. To reduce power, we therefore have to pay special
attention to global wiring capacitances.
3. Low-Power Design Techniques:
An integrated low power methodology requires optimization at all design abstraction layers as
mentioned below.
1. System: Partitioning, Power down
2. Algorithm: Complexity, Concurrency, Regularity
3. Architecture: Parallelism, Pipelining, Redundancy, Data Encoding
4. Circuit Logic: Logic Styles, Energy Recovery, Transistor Sizing
5. Technology: Threshold Reduction, Multithreshold Devices.
4. Power reduction techniques at circuit level:.
The power reduction techniques at the circuit level are quite limited if compared with the other
techniques at higher abstraction levels, At the circuit level , percentage power reduction in the
teens is considered good. However, circuit techniques can have major impact because some

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circuits, especially in cell- based design, are repeated thousands of times on a chip. Therefore,
circuit techniques with a small percentage improvement should not be overlooked. Circuits
designed manually can often be analyzed in great details. This allows us to optimize the circuit
speed, power and area to suit our specification,
There are different techniques for reducing power at circuit level:
1. Transistor and Gate Sizing of an Inverter
2. Chain Equivalent Pin Ordering
3. Network Restructuring and Reorganization
4. Transistor Network Partitioning and Reorganization
5. Flip Flops & Latches design
6. Self-gating Flip-flop
7. Combinational flip flop
8. Double Edge Triggered flip flop
9. Low Power Digital Cell Library
4.1 Transistor and Gate Sizing
At the circuit level, transistors are the basic building blocks and a digital circuit can be
viewed as a network of transistors with some additional parasitic elements such as
capacitors and resistors. Transistor sizes are the most important factor affecting the
quality ie area, and power dissipation of a circuit.Some studies assume that the sizing
problem is a convex function and linear programming can be used to solve the sizing
problem optimally. Another problem encountered in cell based design is gate sizing. The
goal is to choose a set of gate sizes that best fits the design constraints.
Sizing an Inverter Chain
The simplest transistor sizing problem is that of an inverter chain.
The general design problem is to drive a large capacitive load without excessive delay,
area and power requirements. A large inverter is required to drive the large capacitive
load at the final stage. If the chain is too long, the signal delay will be too large due to
intrinsic delay of each inverter. If the chain is too short, the output signal slope will be
very weak with long rise and fall times, which again causes long delay. The challenge is
to decide the length of the chain ie. How many inverters, and the size of each inverter

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Transistor and Gate Sizing for Dynamic Power Dissipation
As seen in the previous graph, a large gate is required to drive a large load with
acceptable delay but requires more power. This is similar to the classical delay area
tradeoff problem. If we are not allowed to restructure the transistor network, the sizing
for dynamic power reduction generally has the same goal as the area reduction problem
The basic rule is to use the smallest transistors or gates that satisfy the delay constraints
To reduce dynamic power, the gates that toggle with higher frequency should be made
smaller. Although the basic rule sounds simple, the actual sizing problem is very
complicated. Consider a part of the circuit as shown below :
Suppose that the gates are not on the critical delay path and should be sized down
W can size down the first gate, the second gate or both, subject to the available sizes in
the cell library as long as the path delay is not violated. If the path contains many gates,
the optimization problem becomes very complicated.
Stack time
Stack time used to express the timing constraints of the circuit. It is the difference
between the signal required time and signal arivela time at the output of a gate. A
positive stack time mean that the signal arrived earlier than its required time and the gate
can be sized down.
The goal of gate sizing is to adjust the gate sizes such that the stack time of each gate is
as low as possible without any gate having a negative stack i.e. timing violation. The area
minimum sizing problem has been a subject of research in logic synthesis for dozen of
years. Today in top down cell based design environment gate sizing has been much
automated by the logic synthesis system.
Transistor Sizing for Leakage Power Reduction
An interesting problem occurs when the sizing goal is to reduce the leakage power of a
circuit. The leakage current of a transistor increases with decreasing threshold voltage
and channel length. In general, a lower threshold or shorter channel transistor can provide
more saturation current and thus offers a faster transistor. The presents a tradeoff between
leakage power and delay. The leakage power of a digital circuit depends on the logic
state of a circuit.
Consider a simple two transistor inverter. If the output of the inverter is at logic high, the
leakage current of the inverter is determined by the N- transistor that is turned off.
Conversely if the output is low, the leakage current depends on the P- transistor.
In order to suppress the leakage current, we can increase the threshold voltage or the
channel length of the N- transistor. However , by doing so we also increase the delay of

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the inverter because the N- transistor now offers less saturation current when it is turned
ON. If we are fortunate that the falling transition of the inverter is not the critical delay,
we can use skewed transistor sizing method to reduce the leakage power without
incurring any delay penalty. The transistor sizing concept is illustrated below.
4.2 Equivalent Pin Ordering
Most combinational digital logic gates have input pins that logically equivalent
Eg: AND, OR, XOR.
Such gates are use frequently because they are natural to the human thinking process. As
for circuit implementation, the gates are robust and easy to design. Logically equivalent
pins may not have identical circuit characteristics, which means that the pins have
different delay and power consumption. Such property can be exploited for low power
design.
Consider a CMOS NAND gate as shown below:
We examine the condition when the input A is at high logic and the input B switches
from logic low to high. The difference in power dissipation varies depending on various
factors such as capacitances and transistor sizes. To conserve power the inputs should be
connected such that transistors from input A to OUT occur more frequently than
transitions from input B to OUT. This low power technique is known as pin ordering.

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4.3 Network Restructuring and Reorganization
The pin reordering technique is a special case of more general method called transistor
restructuring. In this method, we restructure the transistors of a combinational cell, based
on signal probabilities, to achieve better power efficiency within the allowable timing
constraints.
Transistor Network Restructuring
In CMOS logic design, there is a well known technique in which a Boolean
function composed of AND and OR operators is directly mapped to a complex
transistor network that implements the function.
The mapping steps are as follows:
1. Each variable in the Boolean function corresponds to a pair of P and N
transistors.
2. For the N transistor network, an AND operator corresponds to a serial
connection and an OR operator corresponds to a parallel connection.
3. For the P transistor network, the composition rule is inverted.
4. An inverter is optionally added to the output of the complex gate to maintain
the proper polarity or to ensure signal strength.

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Power reduction up to 20% was reported using the transistor network
restructuring technique .
4.4 Transistor Network Partitioning and Reorganization
In this section, we look beyond a CMOS gate and consider a transistor network.
We study the problem of partitioning and reorganizing the network to explore the
different power-area-delay trade off.
Network reorganization by definition is the task of composing different transistor
networks that can implement the same functionality.
The figure below show two ways to implement a 4 input AND operation with a serial
chain limit of three .
4.5 Flip Flops & Latches design
Flip flops and latches are some of the most frequently used elements in digital VLSI
In synchronous systems, they are the starting and ending points of signal delay paths,
which decide the maximum speed of the system. Typically, they consume more power
because they are clocked at the system operating frequency. Careful design of the flip
flop and latch circuits is important to a low power VLSI design.
The energy dissipation of a flip flop can be divided into two components:
1. Clock energy
2. Data energy
The first component is the energy dissipated when the flip flop is clocked while the data
of the flip flop is unchanged. The second component is the additional energy required to
write a different data value into flip flop. In a typical flip flop the two energy components
are comparable. However, in most systems, the data rate of a flip flop is typically much
lower than its clock rate.
This means that identical data values is being loaded with very high probability
Thus, the power saving techniques for flip flops mostly concentrate on the clock energy
reduction. The figure below shows various implementation of CMOS latches.
The circuits shown in fig. provides a different tradeoff among setup time, hold time, data to

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output and clock to output delay. The use of NMOS pass transistors instead of transmission
gates reduces the loading capacitance of the clock pin at the cost of reduced speed ,this
eliminates the need for a two phase non overlapping clock on the system or a phase
splitter inverter that consumes power inside the cell.
This circuit suffers from threshold voltage loss when logic 1 is propagated through the
NMOS pass transistor. The single phase latch circuit avoids the threshold voltage
problem but relies on charge storage effect to retain its data value. This cause some loss
in the noise margin but the circuit has been successfully used in high performance
processor design. The figure below shows some circuit configuration of flip flops:
A flip flop is typically constructed from two latches connected together. The single phase dynamic
flip flop at the top left is a cascaded version of two single phase latches. It is suitable for
some low power applications because it does not require internal phase splitting inverter for

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the clock pin. The circuit at the bottom was reported to achieve lower power at the same
speed with more transistors, compared to a standard flip flop design on the top right. One
circuit that an exotic differential signaling method to increase speed at the expense of area
and power is shown as:
4.6 Self-gating Flip-flop:
Self gating is a popular technique reducing the power in synchronous circuit. it is the
part of the clock energy of a flip flop is consumed by the internal clock buffer to control
the transmission gates. If the input of the flip flop is identical to its output, the switching
of its clock signal can be suppressed to conserve power , this is similar to clock gating
techniques. The difference is that the gating function is derived within the flip flop
without any external control signal. Power is saved by holding the internal clock signals
of the flip flop when allowed. The external clock signal of the flip flop still switches .An
example of self gating flip flop is shown below:

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4.7 Combinational flip flop:
One way to reduce circuit size is to associate logic gates with a flip flop to produce a
combinational flip flop. Combinational flip flops are efficient because they are able to
eliminate or share redundant gates. In terms of area, power and delay, combinational flip
flops are desirable but they increase the design complexity.
4.8 Double Edge Triggered flip flop
Most flip flops in use today are called single edge triggered flip flop (SETFF) because the
data are loaded at only one clock edge, either rising or falling
A flip flop can also be designed so that it loads data at both rising and falling clock edges

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4.9 Low Power Digital Cell Library:
Over the years, the major VLSI design focus has shifted from masks, to transistors, to
gates and to register transfer level. Undoubtedly, the quality of gate level circuit
synthesized depends on the quality of the cell library.
Cell Sizes and Spacing
In the top-down cell based design methodology, the tradeoff among power, area
and delay is performed by selecting the appropriate sizes of the cells. Therefore,
the important attribute that constitute a good low power cell library is the
availability of wide ranges of cell sizes for commonly used gates. Further, the
library cell count can be reduced without too much compromise in quality is to
have more size selections for gates that are commonly used than those are less
likely used.
Varieties of Boolean Functions
The lack of varieties of Boolean functions in a cell library can result in inferior
circuits to be generated. For example if the Boolean function were to be
implemented and the inverted input cells are not available, the logic synthesis
system has to use an INVERTER and an AND gate to implement the function.
The two cell implementation is less power efficient compared to the single cell
implementation because of the external routing capacitance at the output of the
inverter.

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5. Conclusion:
Power consumption has become a critical design parameter for both high-performance and
portable applications. Power therefore has to be reduced at all stages of the design flow, from
system/algorithmic level down to the physical level. We have discussed the different parameters
affecting the power consumption of digital designs, and how they can be reduced at circuit
levels during circuit design, and what improvements these optimizations can yield.
So, This report reviewed that how power consumption take place at circuit
level and a number of techniques for low power design of VLSI circuits at circuit level
synthesis.

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6. References
1. Practical Low Power Digital VLSI Design by Gary K. Yeap
2. Low-Power CMOS VLSI Circuit Design by Kaushik Roy and Sharat C. Prasad
3. http://www.eeherald.com/section/design-guide/Low-Power-VLSI-Design.html