Arteris NoC SoC Interconnect presentation given by Jonah Probell at ARM Technology Conference 9-11 Nov 2010. Explains how traditional AXI fabrics require huge numbers of wires and leads to routing congestion, and how network on chip interconnects address routing congestion by allowing fewer wires. Explains the basics of NoC packetization and serialization.

1. November 9-11, 2010 The Santa Clara Convention Center www.armtechcon.com

2. P&R congestion is the focus of EDA "...upstream tools need to be claivoyant deep into the layout." "The worst crises are when you're deep into the layout and realize that my floorplan's no good. So how do you avoid that? Well what's needed are claivoyant tools. That is a chain of steps where each step already knows a little bit about the changes downstream." "The synthesizer can, this year, avoid congestion; and congestion is really the killer of schedules.“ -Aart DeGeus, Synopsys Synposium 2010

3. Interconnects logically Interconnect The interconnect transports AXI transactions between masters and slaves. The means of transportation are not defined by the AXI spec. master master master master master slave slave slave slave slave AXI AXI

4. Interconnect physically The interconnect lives in the hallways between IP cores. The width of the links affects the compactness of the die.

5. 1. Growing interface complexity Address Write data Read data Write address Write data Read data Read address Write response 32 Data width Data width 32 Data width Data width 32 Control A few Wires Wires Control A few Control A few Control A few Control A few A few AHB AXI Signal Signal Data width 32 64 128 AHB signals 113 177 305 AXI signals 204 272 408

6. 2. More interfaces each year

7. 3. Relative wire cost growing Transistor sizes shrink faster than wire widths. 286 CPU (1982) 69 mm 2 Atom N450 (2010) 66 mm 2 Chips are, on average, the same size as ever.

9. Packetizing AXI to transport transactions Read Address Read Data Write Data Write Address Write Response Request from master Response to master Request Packet Response Packet packetize depacketize

10. Packetizing AXI to transport transactions Read Address Read Data Write Data Write Address Write Response Request to slave Response to master Request Packet Response Packet depacketize packetize

11. Serializing With a packetized protocol, serializing data simply requires a register and a mux. Serializing packets is much easier than serializing the AXI interface protocol.

12. Throughput and wires header data data header data data data data header data data data data header header data data (a) (b) (c) (d) Link width = data width + header width Header penalty = 0 Link width = header width Header penalty = 1 cycle per transaction Link width < data width Header penalty > 1 cycle per transaction Link width = data width Header penalty = 1 cycle per transaction

13. Selection of link width L2 DDR peripherals Place cores with high communication throughput and low latency requirements near each other. Use zero header penalty links between such cores. Use narrow links for long paths to low throughput peripherals. This minimizes the number of long wires for P&R

14. Experimental packetized link width results obtained with Arteris FlexNoC packetized interconnect generator Data width 32 64 128 AHB signals 113 177 305 AXI signals 204 272 408 Packets with 0 penalty cycles 146 218 362 Packets with 1 penalty cycle 84 156 300

15. Experimental place & route results Standard NoC

16. Summary Routing congestion is the problem of the decade for chip implementation. AXI is expensive in wires. Packetizing and serializing transaction data effectively reduces routing congestion.

17. Clairvoyant IP physical synthesis P&R RTL serializing interconnect -> fewer wires physical synthesis -> shorter wires