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Speech Reognition Using FPGA Technology

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Carlos
Carlos

The document describes a student project to implement speech recognition using FPGA technology. It aims to identify single words in a hardware system that is cost-effective, reliable and simple. Background theory on speech recognition is provided, including how sounds are converted to fingerprints using FFT and averaged amplitudes in the frequency domain for training. MATLAB code was created to test the concept before hardware implementation.

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101010101010101010101 010111100101011001011 Speech Recognition 110101010101010101001 010100101010100110111 010100101001010001010 Using FPGA Technology 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 By 001010001010101010101 101010111010010101001 Carlos Asmat 260148251 010111100101011001011 David López Sansò 260146414 110101010101010101001 Kanwen Wu 260045745 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 Project Coordinator: Prof. Kenneth L. Fraser 010100110111010100101 110101010101010101001 Project Supervisor: Prof. Miguel Marin 010100101010100110111 010100101001010001010 Presentation Date: Wednesday, June 6, 2007 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 010100101001010001010 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Outline 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 1) Introduction 101010001010111011000 101101011000110100101 010100110111010100101 2) MATLAB™ Demonstration 001010001010101010101 101010111010010101001 010111100101011001011 3) Hardware Implementation 110101010101010101001 010100101010100110111 010101010001110101110 4) Hardware Demonstration 101010001010111011000 101101011000110100101 010100110111010100101 5) Final remarks 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 010100101001010001010 2 101010101101010101011 Carlos Asmat – David López Sanzò – Kanwen Wu
101010101010101010101 010111100101011001011 What is speech recognition? 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Convert analog sound into binary digits. 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 ● Compare with the pre-stored word. 101010111010010101001 010111100101011001011 110101010101010101001 speaker 010100101010100110111 ● Not to confuse with recognition. 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 3 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 110101010101010101001 Speech Recognition Performance 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Priority: Accuracy and Reliability. 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 ● Consumer products. 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 4 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Objectives 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Hardware implementation of a simple speech recognition 101010001010111011000 101101011000110100101 system. 010100110111010100101 001010001010101010101 101010111010010101001 ● Single word identification. 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 ● Cost efficiency, reliability, and simplicity are the major 101010001010111011000 consideration. 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks010100101001010001010 5 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● The sound identification is based on its frequency content. 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 ● Two steps: 101010111010010101001 010111100101011001011 ➔ Training 110101010101010101001 010100101010100110111 ➔ Recognition 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 6 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Background theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● A MATLAB™ implementation was devised to assess the 101010001010111011000 101101011000110100101 project feasibility. 010100110111010100101 001010001010101010101 101010111010010101001 ● Two files were produced: 010111100101011001011 110101010101010101001 010100101010100110111 ➔ train.m 010101010001110101110 101010001010111011000 ➔ recogniz.m 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 7 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Training: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ Input several versions of a sound. 001010001010101010101 101010111010010101001 ➔ Translate them to the frequency domain by using the 010111100101011001011 FFT. 110101010101010101001 010100101010100110111 ➔ Average their amplitude in the frequency domain. 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 fingerprint. ● This produces the sound's 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 8 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Note on the FFT: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ Only half of it is used. 001010001010101010101 101010111010010101001 ➔ Five 1024-points FFTs are performed per sound 010111100101011001011 sample. 110101010101010101001 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 −2 i N −1 010100110111010100101 nk X =∑ x e N k =0,... , N −1 110101010101010101001 k n 010100101010100110111 n=0 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 9 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● User inputs .wav files. 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 ● Decimate and quantize the input sound files. 101010111010010101001 010111100101011001011 110101010101010101001 ● Sound acquisition parameters: 010100101010100110111 010101010001110101110 101010001010111011000 ➔ Sound samples are quantized down to 101101011000110100101 8 bits. 010100110111010100101 ➔ The sampling frequency is 5 kHz. 110101010101010101001 010100101010100110111 ➔ Around one second (1.024s) of sound is stored. 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 10 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Sound detection: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ Compute the average of a window. 001010001010101010101 101010111010010101001 ➔ Compare it to the average of the next window. 010111100101011001011 110101010101010101001 ➔ If the difference is significant then the 010100101010100110111 sound is assumed to start at that point. 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks010100101001010001010 11 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Sound detection (cont'd): 101010001010111011000 101101011000110100101 010100110111010100101 w =w =1024 samples 001010001010101010101 1 2 101010111010010101001 =0.2048s 010111100101011001011 110101010101010101001 L=5120 samples=1.024s 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 12 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Store detected sound stream into a vector. 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 ● Apply FFT to the above vector's first 1024 101010111010010101001 points and put it in 's'. 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 ● Store 's' as the first row in the matrix 'x' and repeat with the 101010001010111011000 following 1024 points until there are five rows in 'x'. 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 13 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Sound recognition: 101010001010111011000 101101011000110100101 ➔ Compute the fingerprint of a sound. 010100110111010100101 001010001010101010101 101010111010010101001 ➔ Compute the distance between the sound's fingerprint 010111100101011001011 and the reference fingerprint 110101010101010101001 010100101010100110111 ➔ If both are close enough, then the sound is assumed to 010101010001110101110 101010001010111011000 match the reference sound. 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks010100101001010001010 14 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Note on the distance computation: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ The sounds fingerprint and the reference fingerprint 001010001010101010101 are considered as 1024-dimensional vectors. 101010111010010101001 010111100101011001011 ➔ The distance between them is computed using the 110101010101010101001 010100101010100110111 euclidean distance formula: 010101010001110101110 101010001010111011000 101101011000110100101  1024 010100110111010100101 2 ∑  a −b  D= 110101010101010101001 i i 010100101010100110111 i=0 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 15 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 System Overview 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 16 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Hardware Implementation 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Design approach 101010001010111011000 101101011000110100101 010100110111010100101 ● A/D Conversion 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 ● Word detector 010100101010100110111 010101010001110101110 101010001010111011000 ● FFT 101101011000110100101 010100110111010100101 110101010101010101001 ● Memory Management 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Distance Computation 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 17 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Design Approach 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Quartus II 101010001010111011000 101101011000110100101 010100110111010100101 ➔ VHDL process blocks 001010001010101010101 101010111010010101001 ➔ Computer-Aided Design 010111100101011001011 110101010101010101001 010100101010100110111 ● Datapath/Overall Controller 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 ● Intermediate controllers 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 18 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 A/D Conversion 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 Source: http://www.societyofrobots.com/images/analogdigital.jpg 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 19 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 A/D – Overall Configuration 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 2 I C Bus 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 MCLK 101010111010010101001 010111100101011001011 BCLK 110101010101010101001 010100101010100110111 Wolfson010101010001110101110 FPGA LRCLK CODEC 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 ADCDAT 010100101010100110111 010100101001010001010 101010101101010101011 MASTER SLAVE 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 20 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 A/D Conversion 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 LINEIN 101010001010111011000 Digital Filters 101101011000110100101 MUX A/D D/A LINEOUT 010100110111010100101 MICIN MUTE 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 010100101010100110111 MUTEMIC INSEL ADCDAT 010101010001110101110 101010001010111011000 ● Internal signals set by bus. 101101011000110100101 010100110111010100101 ➔ De-mute. 110101010101010101001 010100101010100110111 ➔ Boost mic. 010100101001010001010 101010101101010101011 010101010001110101110 ➔ Change path. 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 21 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 2 I C Bus 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 Source: Wolfson WM8731 data sheets, p.43 110101010101010101001 010100101010100110111 010101010001110101110 ● RADDR → Base address = 0011010 101010001010111011000 101101011000110100101 ● R/W → Read/Write =0 010100110111010100101 110101010101010101001 010100101010100110111 ● B[15-9] → Control Address = 0000100 010100101001010001010 101010101101010101011 ● B[8-0] → Control Data = 000001101 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 22 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 2 I C Bus 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 Source: Wolfson WM8731 data sheets, p.43 110101010101010101001 010100101010100110111 'MIC BOOST' 010101010001110101110 101010001010111011000 'MUTE MIC' 101101011000110100101 010100110111010100101 'INSEL' 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 ● B[8-0] → Control Data = 000001101 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 23 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 2 I C Bus – ACK Signal 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● ACK signal goes from the Wolfson to the FPGA 101010001010111011000 101101011000110100101 ➔ Opposite direction from rest of data 010100110111010100101 001010001010101010101 101010111010010101001 ➔ Only one data line 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 24 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 2 I C Bus – ACK Signal 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● ACK signal goes from the Wolfson to the FPGA 101010001010111011000 101101011000110100101 ➔ Opposite direction from rest of data 010100110111010100101 001010001010101010101 101010111010010101001 ➔ Only one data line 010111100101011001011 110101010101010101001 010100101010100110111 Solution... 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 25 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 2 I C Bus – ACK Signal 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● ACK signal goes from the Wolfson to the FPGA 101010001010111011000 101101011000110100101 ➔ Opposite direction from rest of data 010100110111010100101 001010001010101010101 101010111010010101001 ➔ Only one data line 010111100101011001011 110101010101010101001 010100101010100110111 Solution... L P M _ B U S T R I e010101010001110101110 n a b le d t 101010001010111011000 d a ta [] 101101011000110100101 010100110111010100101 110101010101010101001 Tri-state buffer! t r id a t a [ ] r e s u lt [ ] 010100101010100110111 010100101001010001010 101010101101010101011 e n a b le t r 010101010001110101110 in s t 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 26 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 A/D – ADCDAT Fetcher 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 Source: Wolfson WM8731 data sheets, p.34 010100110111010100101 110101010101010101001 ● Clock module 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 nd ● MSB available on 2 rising BCLK edge 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 27 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Quantization 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Codec output: two's complement 101010001010111011000 101101011000110100101 ● Quantize 24 bits into 8. Decimal Binary Quantized Quantized 010100110111010100101 number (2's comp.) 001010001010101010101 binary decimal 101010111010010101001 (2's comp.) 010111100101011001011 3 011 110101010101010101001 01 1 010100101010100110111 2 010 010101010001110101110 101010001010111011000 1 001 101101011000110100101 00 0 0 000 010100110111010100101 110101010101010101001 -1 111 010100101010100110111 11 -1 010100101001010001010 -2 110 101010101101010101011 -3 101 010101010001110101110 10 -2 101010001010111011000 -4 100 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 28 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Downsampler 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 DATA_IN @ 48 kHz DATA_OUT@ 5 kHz Downsampler 010100110111010100101 001010001010101010101 101010111010010101001 READY 010111100101011001011 110101010101010101001 010100101010100110111 ● Implementation 010101010001110101110 101010001010111011000 101101011000110100101 ➔ Flip-flop 010100110111010100101 110101010101010101001 ➔ Counters (and FSM) 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 29 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Word Detector 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 8 9 Average DATA_IN 101010001010111011000 Absolute 101101011000110100101 Register 2 Difference 010100110111010100101 001010001010101010101 Register 1 101010111010010101001 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 Comparator SOUND_STARTS 101010001010111011000 101101011000110100101 010100110111010100101 9 110101010101010101001 ● Detects sharp transitions. THRESHOLD 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 30 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Fast Fourier Transform 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ® ● Altera IP MegaCore 1024-points FFT module: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ Natural order streaming data input. 001010001010101010101 101010111010010101001 ➔ Bit-reversed streaming data output. 010111100101011001011 110101010101010101001 ➔ Low latency. FFT 010100101010100110111 c lk 010101010001110101110 s in k _ r e a d y ➔ Time Limited Version. re s e t_ n s o u rc e _ e rro r[1 ..0 ] 101010001010111011000 in v e r s e s o u rc e _ s o p 101101011000110100101 s in k _ v a lid s o u rc e _ e o p 010100110111010100101 s in k _ s o p s o u r c e _ v a lid 110101010101010101001 s in k _ e o p s o u rc e _ e x p [5 ..0 ] 010100101010100110111 s in k _ r e a l[ 7 . . 0 ] s o u r c e _ r e a l[ 7 . . 0 ] s in k _ im a g [ 7 . . 0 ] s o u r c e _ im a g [ 7 . . 0 ] 010100101001010001010 s in k _ e r r o r [ 1 . . 0 ] 101010101101010101011 s o u rc e _ re a d y 010101010001110101110 101010001010111011000 in s t 1 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 31 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Memory Management 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Three memory modules: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ FALSH (4MB) 001010001010101010101 101010111010010101001 ➔ SDRAM (8MB) 010111100101011001011 110101010101010101001 ➔ SRAM (512 kB) 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 32 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Memory Management 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● 512 kB SRAM memory module 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 18 101010111010010101001 Address 010111100101011001011 110101010101010101001 Chip Enable 010100101010100110111 Write Enable 16 010101010001110101110 SRAM Chip Data I/O 101010001010111011000 Output Enable 101101011000110100101 High Byte Mask 010100110111010100101 110101010101010101001 Low Byte Mask 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 33 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Memory Management 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 16 bits ● Memory structure: 101010001010111011000 101101011000110100101 0 1 0 010100110111010100101 2 3 1 001010001010101010101 2 4 5 101010111010010101001 3 6 7 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 18 2 blocks 101010001010111011000 101101011000110100101 010100110111010100101 262 141 110101010101010101001 524 280 524 281 262 142 010100101010100110111 524 282 524 283 262 143 010100101001010001010 524 284 524 285 101010101101010101011 262 144 524 287 524 288 010101010001110101110 101010001010111011000 8 bits 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 34 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Memory Management 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Memory Controller: 101010001010111011000 101101011000110100101 19 ADDR 010100110111010100101 001010001010101010101 8 8101010111010010101001 DATA_IN DATA_OUT Memory Controller 010111100101011001011 MODE 110101010101010101001 ENABLE 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 18 16 010100110111010100101 110101010101010101001 High Byte Mask Low Byte Mask 010100101010100110111 Output Enable Write Enable Chip Enable 010100101001010001010 101010101101010101011 Data I/O Address 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 35 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
101010101010101010101 010111100101011001011 Memory Management 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Batch Operations: 101010001010111011000 101101011000110100101 010100110111010100101 19 001010001010101010101 START_ADDR 101010111010010101001 19 010111100101011001011 END_ADDR 8 110101010101010101001 DATA_OUT 8 010100101010100110111 DATA_IN 010101010001110101110 Memory MEM_MODE 101010001010111011000 Batch Operator MODE 101101011000110100101 MEM_ENABLE 19 DATA_READY 010100110111010100101 ADDR 110101010101010101001 ENABLE 010100101010100110111 010100101001010001010 CLK 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 36 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
Speech Reognition Using FPGA Technology
Speech Reognition Using FPGA Technology
Speech Reognition Using FPGA Technology
Speech Reognition Using FPGA Technology
Speech Reognition Using FPGA Technology
Speech Reognition Using FPGA Technology
Speech Reognition Using FPGA Technology

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Speech Reognition Using FPGA Technology

  • 1. 101010101010101010101 010111100101011001011 Speech Recognition 110101010101010101001 010100101010100110111 010100101001010001010 Using FPGA Technology 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 By 001010001010101010101 101010111010010101001 Carlos Asmat 260148251 010111100101011001011 David López Sansò 260146414 110101010101010101001 Kanwen Wu 260045745 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 Project Coordinator: Prof. Kenneth L. Fraser 010100110111010100101 110101010101010101001 Project Supervisor: Prof. Miguel Marin 010100101010100110111 010100101001010001010 Presentation Date: Wednesday, June 6, 2007 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 010100101001010001010 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 2. 101010101010101010101 010111100101011001011 Outline 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 1) Introduction 101010001010111011000 101101011000110100101 010100110111010100101 2) MATLAB™ Demonstration 001010001010101010101 101010111010010101001 010111100101011001011 3) Hardware Implementation 110101010101010101001 010100101010100110111 010101010001110101110 4) Hardware Demonstration 101010001010111011000 101101011000110100101 010100110111010100101 5) Final remarks 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 010100101001010001010 2 101010101101010101011 Carlos Asmat – David López Sanzò – Kanwen Wu
  • 3. 101010101010101010101 010111100101011001011 What is speech recognition? 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Convert analog sound into binary digits. 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 ● Compare with the pre-stored word. 101010111010010101001 010111100101011001011 110101010101010101001 speaker 010100101010100110111 ● Not to confuse with recognition. 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 3 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 4. 101010101010101010101 010111100101011001011 110101010101010101001 Speech Recognition Performance 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Priority: Accuracy and Reliability. 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 ● Consumer products. 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 4 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 5. 101010101010101010101 010111100101011001011 Objectives 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Hardware implementation of a simple speech recognition 101010001010111011000 101101011000110100101 system. 010100110111010100101 001010001010101010101 101010111010010101001 ● Single word identification. 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 ● Cost efficiency, reliability, and simplicity are the major 101010001010111011000 consideration. 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks010100101001010001010 5 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 6. 101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● The sound identification is based on its frequency content. 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 ● Two steps: 101010111010010101001 010111100101011001011 ➔ Training 110101010101010101001 010100101010100110111 ➔ Recognition 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 6 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 7. 101010101010101010101 010111100101011001011 Background theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● A MATLAB™ implementation was devised to assess the 101010001010111011000 101101011000110100101 project feasibility. 010100110111010100101 001010001010101010101 101010111010010101001 ● Two files were produced: 010111100101011001011 110101010101010101001 010100101010100110111 ➔ train.m 010101010001110101110 101010001010111011000 ➔ recogniz.m 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 7 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 8. 101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Training: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ Input several versions of a sound. 001010001010101010101 101010111010010101001 ➔ Translate them to the frequency domain by using the 010111100101011001011 FFT. 110101010101010101001 010100101010100110111 ➔ Average their amplitude in the frequency domain. 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 fingerprint. ● This produces the sound's 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 8 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 9. 101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Note on the FFT: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ Only half of it is used. 001010001010101010101 101010111010010101001 ➔ Five 1024-points FFTs are performed per sound 010111100101011001011 sample. 110101010101010101001 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 −2 i N −1 010100110111010100101 nk X =∑ x e N k =0,... , N −1 110101010101010101001 k n 010100101010100110111 n=0 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 9 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 10. 101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● User inputs .wav files. 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 ● Decimate and quantize the input sound files. 101010111010010101001 010111100101011001011 110101010101010101001 ● Sound acquisition parameters: 010100101010100110111 010101010001110101110 101010001010111011000 ➔ Sound samples are quantized down to 101101011000110100101 8 bits. 010100110111010100101 ➔ The sampling frequency is 5 kHz. 110101010101010101001 010100101010100110111 ➔ Around one second (1.024s) of sound is stored. 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 10 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 11. 101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Sound detection: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ Compute the average of a window. 001010001010101010101 101010111010010101001 ➔ Compare it to the average of the next window. 010111100101011001011 110101010101010101001 ➔ If the difference is significant then the 010100101010100110111 sound is assumed to start at that point. 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks010100101001010001010 11 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 12. 101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Sound detection (cont'd): 101010001010111011000 101101011000110100101 010100110111010100101 w =w =1024 samples 001010001010101010101 1 2 101010111010010101001 =0.2048s 010111100101011001011 110101010101010101001 L=5120 samples=1.024s 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 12 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 13. 101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Store detected sound stream into a vector. 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 ● Apply FFT to the above vector's first 1024 101010111010010101001 points and put it in 's'. 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 ● Store 's' as the first row in the matrix 'x' and repeat with the 101010001010111011000 following 1024 points until there are five rows in 'x'. 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 13 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 14. 101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Sound recognition: 101010001010111011000 101101011000110100101 ➔ Compute the fingerprint of a sound. 010100110111010100101 001010001010101010101 101010111010010101001 ➔ Compute the distance between the sound's fingerprint 010111100101011001011 and the reference fingerprint 110101010101010101001 010100101010100110111 ➔ If both are close enough, then the sound is assumed to 010101010001110101110 101010001010111011000 match the reference sound. 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks010100101001010001010 14 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 15. 101010101010101010101 010111100101011001011 Background Theory 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Note on the distance computation: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ The sounds fingerprint and the reference fingerprint 001010001010101010101 are considered as 1024-dimensional vectors. 101010111010010101001 010111100101011001011 ➔ The distance between them is computed using the 110101010101010101001 010100101010100110111 euclidean distance formula: 010101010001110101110 101010001010111011000 101101011000110100101  1024 010100110111010100101 2 ∑  a −b  D= 110101010101010101001 i i 010100101010100110111 i=0 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 15 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 16. 101010101010101010101 010111100101011001011 System Overview 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 16 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 17. 101010101010101010101 010111100101011001011 Hardware Implementation 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Design approach 101010001010111011000 101101011000110100101 010100110111010100101 ● A/D Conversion 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 ● Word detector 010100101010100110111 010101010001110101110 101010001010111011000 ● FFT 101101011000110100101 010100110111010100101 110101010101010101001 ● Memory Management 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Distance Computation 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 17 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 18. 101010101010101010101 010111100101011001011 Design Approach 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Quartus II 101010001010111011000 101101011000110100101 010100110111010100101 ➔ VHDL process blocks 001010001010101010101 101010111010010101001 ➔ Computer-Aided Design 010111100101011001011 110101010101010101001 010100101010100110111 ● Datapath/Overall Controller 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 ● Intermediate controllers 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 18 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 19. 101010101010101010101 010111100101011001011 A/D Conversion 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 Source: http://www.societyofrobots.com/images/analogdigital.jpg 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 19 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 20. 101010101010101010101 010111100101011001011 A/D – Overall Configuration 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 2 I C Bus 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 MCLK 101010111010010101001 010111100101011001011 BCLK 110101010101010101001 010100101010100110111 Wolfson010101010001110101110 FPGA LRCLK CODEC 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 ADCDAT 010100101010100110111 010100101001010001010 101010101101010101011 MASTER SLAVE 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 20 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 21. 101010101010101010101 010111100101011001011 A/D Conversion 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 LINEIN 101010001010111011000 Digital Filters 101101011000110100101 MUX A/D D/A LINEOUT 010100110111010100101 MICIN MUTE 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 010100101010100110111 MUTEMIC INSEL ADCDAT 010101010001110101110 101010001010111011000 ● Internal signals set by bus. 101101011000110100101 010100110111010100101 ➔ De-mute. 110101010101010101001 010100101010100110111 ➔ Boost mic. 010100101001010001010 101010101101010101011 010101010001110101110 ➔ Change path. 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 21 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 22. 101010101010101010101 010111100101011001011 2 I C Bus 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 Source: Wolfson WM8731 data sheets, p.43 110101010101010101001 010100101010100110111 010101010001110101110 ● RADDR → Base address = 0011010 101010001010111011000 101101011000110100101 ● R/W → Read/Write =0 010100110111010100101 110101010101010101001 010100101010100110111 ● B[15-9] → Control Address = 0000100 010100101001010001010 101010101101010101011 ● B[8-0] → Control Data = 000001101 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 22 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 23. 101010101010101010101 010111100101011001011 2 I C Bus 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 Source: Wolfson WM8731 data sheets, p.43 110101010101010101001 010100101010100110111 'MIC BOOST' 010101010001110101110 101010001010111011000 'MUTE MIC' 101101011000110100101 010100110111010100101 'INSEL' 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 ● B[8-0] → Control Data = 000001101 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 23 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 24. 101010101010101010101 010111100101011001011 2 I C Bus – ACK Signal 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● ACK signal goes from the Wolfson to the FPGA 101010001010111011000 101101011000110100101 ➔ Opposite direction from rest of data 010100110111010100101 001010001010101010101 101010111010010101001 ➔ Only one data line 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 24 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 25. 101010101010101010101 010111100101011001011 2 I C Bus – ACK Signal 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● ACK signal goes from the Wolfson to the FPGA 101010001010111011000 101101011000110100101 ➔ Opposite direction from rest of data 010100110111010100101 001010001010101010101 101010111010010101001 ➔ Only one data line 010111100101011001011 110101010101010101001 010100101010100110111 Solution... 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 25 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 26. 101010101010101010101 010111100101011001011 2 I C Bus – ACK Signal 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● ACK signal goes from the Wolfson to the FPGA 101010001010111011000 101101011000110100101 ➔ Opposite direction from rest of data 010100110111010100101 001010001010101010101 101010111010010101001 ➔ Only one data line 010111100101011001011 110101010101010101001 010100101010100110111 Solution... L P M _ B U S T R I e010101010001110101110 n a b le d t 101010001010111011000 d a ta [] 101101011000110100101 010100110111010100101 110101010101010101001 Tri-state buffer! t r id a t a [ ] r e s u lt [ ] 010100101010100110111 010100101001010001010 101010101101010101011 e n a b le t r 010101010001110101110 in s t 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 26 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 27. 101010101010101010101 010111100101011001011 A/D – ADCDAT Fetcher 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 101010111010010101001 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 Source: Wolfson WM8731 data sheets, p.34 010100110111010100101 110101010101010101001 ● Clock module 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 nd ● MSB available on 2 rising BCLK edge 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 27 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 28. 101010101010101010101 010111100101011001011 Quantization 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Codec output: two's complement 101010001010111011000 101101011000110100101 ● Quantize 24 bits into 8. Decimal Binary Quantized Quantized 010100110111010100101 number (2's comp.) 001010001010101010101 binary decimal 101010111010010101001 (2's comp.) 010111100101011001011 3 011 110101010101010101001 01 1 010100101010100110111 2 010 010101010001110101110 101010001010111011000 1 001 101101011000110100101 00 0 0 000 010100110111010100101 110101010101010101001 -1 111 010100101010100110111 11 -1 010100101001010001010 -2 110 101010101101010101011 -3 101 010101010001110101110 10 -2 101010001010111011000 -4 100 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 28 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 29. 101010101010101010101 010111100101011001011 Downsampler 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 101101011000110100101 DATA_IN @ 48 kHz DATA_OUT@ 5 kHz Downsampler 010100110111010100101 001010001010101010101 101010111010010101001 READY 010111100101011001011 110101010101010101001 010100101010100110111 ● Implementation 010101010001110101110 101010001010111011000 101101011000110100101 ➔ Flip-flop 010100110111010100101 110101010101010101001 ➔ Counters (and FSM) 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 29 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 30. 101010101010101010101 010111100101011001011 Word Detector 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 8 9 Average DATA_IN 101010001010111011000 Absolute 101101011000110100101 Register 2 Difference 010100110111010100101 001010001010101010101 Register 1 101010111010010101001 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 Comparator SOUND_STARTS 101010001010111011000 101101011000110100101 010100110111010100101 9 110101010101010101001 ● Detects sharp transitions. THRESHOLD 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 30 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 31. 101010101010101010101 010111100101011001011 Fast Fourier Transform 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ® ● Altera IP MegaCore 1024-points FFT module: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ Natural order streaming data input. 001010001010101010101 101010111010010101001 ➔ Bit-reversed streaming data output. 010111100101011001011 110101010101010101001 ➔ Low latency. FFT 010100101010100110111 c lk 010101010001110101110 s in k _ r e a d y ➔ Time Limited Version. re s e t_ n s o u rc e _ e rro r[1 ..0 ] 101010001010111011000 in v e r s e s o u rc e _ s o p 101101011000110100101 s in k _ v a lid s o u rc e _ e o p 010100110111010100101 s in k _ s o p s o u r c e _ v a lid 110101010101010101001 s in k _ e o p s o u rc e _ e x p [5 ..0 ] 010100101010100110111 s in k _ r e a l[ 7 . . 0 ] s o u r c e _ r e a l[ 7 . . 0 ] s in k _ im a g [ 7 . . 0 ] s o u r c e _ im a g [ 7 . . 0 ] 010100101001010001010 s in k _ e r r o r [ 1 . . 0 ] 101010101101010101011 s o u rc e _ re a d y 010101010001110101110 101010001010111011000 in s t 1 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 31 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 32. 101010101010101010101 010111100101011001011 Memory Management 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Three memory modules: 101010001010111011000 101101011000110100101 010100110111010100101 ➔ FALSH (4MB) 001010001010101010101 101010111010010101001 ➔ SDRAM (8MB) 010111100101011001011 110101010101010101001 ➔ SRAM (512 kB) 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 010100110111010100101 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 32 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 33. 101010101010101010101 010111100101011001011 Memory Management 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● 512 kB SRAM memory module 101010001010111011000 101101011000110100101 010100110111010100101 001010001010101010101 18 101010111010010101001 Address 010111100101011001011 110101010101010101001 Chip Enable 010100101010100110111 Write Enable 16 010101010001110101110 SRAM Chip Data I/O 101010001010111011000 Output Enable 101101011000110100101 High Byte Mask 010100110111010100101 110101010101010101001 Low Byte Mask 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 33 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 34. 101010101010101010101 010111100101011001011 Memory Management 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 16 bits ● Memory structure: 101010001010111011000 101101011000110100101 0 1 0 010100110111010100101 2 3 1 001010001010101010101 2 4 5 101010111010010101001 3 6 7 010111100101011001011 110101010101010101001 010100101010100110111 010101010001110101110 18 2 blocks 101010001010111011000 101101011000110100101 010100110111010100101 262 141 110101010101010101001 524 280 524 281 262 142 010100101010100110111 524 282 524 283 262 143 010100101001010001010 524 284 524 285 101010101101010101011 262 144 524 287 524 288 010101010001110101110 101010001010111011000 8 bits 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 34 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 35. 101010101010101010101 010111100101011001011 Memory Management 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Memory Controller: 101010001010111011000 101101011000110100101 19 ADDR 010100110111010100101 001010001010101010101 8 8101010111010010101001 DATA_IN DATA_OUT Memory Controller 010111100101011001011 MODE 110101010101010101001 ENABLE 010100101010100110111 010101010001110101110 101010001010111011000 101101011000110100101 18 16 010100110111010100101 110101010101010101001 High Byte Mask Low Byte Mask 010100101010100110111 Output Enable Write Enable Chip Enable 010100101001010001010 101010101101010101011 Data I/O Address 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 35 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011
  • 36. 101010101010101010101 010111100101011001011 Memory Management 110101010101010101001 010100101010100110111 010100101001010001010 101010101101010101011 010101010001110101110 ● Batch Operations: 101010001010111011000 101101011000110100101 010100110111010100101 19 001010001010101010101 START_ADDR 101010111010010101001 19 010111100101011001011 END_ADDR 8 110101010101010101001 DATA_OUT 8 010100101010100110111 DATA_IN 010101010001110101110 Memory MEM_MODE 101010001010111011000 Batch Operator MODE 101101011000110100101 MEM_ENABLE 19 DATA_READY 010100110111010100101 ADDR 110101010101010101001 ENABLE 010100101010100110111 010100101001010001010 CLK 101010101101010101011 010101010001110101110 101010001010111011000 110101010101010101001 010100101010100110111 Introduction ● Hardware Implementation ● Demo ● Final Remarks 010100101001010001010 36 Carlos Asmat – David López Sanzò – Kanwen Wu 101010101101010101011