1. Evolution of materials technology for stacked-capacitors
in 65 nm embedded-DRAM
Eric Gerritsen a,*, Nicolas Emonet b
, Christian Caillat b
, Nicolas Jourdan b
,
Marc Piazza b
, David Fraboulet d
, Bruce Boeck c
, Audrey Berthelot a
,
Steven Smith a
, Pascale Mazoyer b
a
Philips Semiconductors, 860 rue Jean Monnet, 38926 Crolles, France
b
STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France
c
Freescale Semiconductor, 870 rue Jean Monnet, 38926 Crolles, France
d
CEA-LETI, 17 rue des Martyrs, 38054 Grenoble, France
Available online 18 November 2005
The review of this paper was arranged by E. Gerritsen, P. Masson and P. Mazoyer
Abstract
The architecture, materials choice and process technology for stacked-capacitors in embedded-DRAM applications are a crucial con-
cern for each new technology node. An overview of the evolution of capacitor technology is presented from the early days of planar PIS
(poly/insulator/silicon) capacitors to the MIM (metal/insulator/metal) capacitors used for todays 65 nm technology node. In comparing
Ta2O5, HfO2 and Al2O3 as high-k dielectric for use in 65 nm eDRAM technology, Al2O3 is found to give a good compromise between
capacitor performance and manufacturability. The use of atomic layer deposition (ALD) is identified to be an enabling technology for
both high-k dielectrics and capacitor electrodes.
Ó 2005 Elsevier Ltd. All rights reserved.
Keywords: DRAM; Capacitor; MIM; High-k; Dielectric; Electrode; Atomic layer deposition, ALD
1. Introduction
A typical DRAM cell consists of an access transistor
and a storage capacitor (1T/1C). There are two types of
storage capacitors, stacked-capacitors and trench capaci-
tors, of which the latter offers highest density, at the
expense of process complexity [1].
Trench capacitors are less suitable for integration of
high-k dielectrics because they are formed before the tran-
sistors with their associated high temperature anneals.
For embedded-DRAM (eDRAM) we have adopted
stacked capacitors as being the most cost-competitive solu-
tion. Because stacked capacitors are formed after the tran-
sistors the overall impact on performance of the CMOS
core process is of primary concern.
If the thermal budget of the capacitor processing is too
high, it will degrade transistor performance.
In the first part of this paper, we will outline the general
evolution of capacitor architectures.
Next we will detail how capacitor materials and process-
ing have evolved from furnace-based polysilicon electrodes
with (oxy)nitride dielectrics towards metallic electrodes
with high-k dielectrics, both processed by atomic layer
deposition (ALD) at moderate thermal budget, favourable
to eDRAM applications.
2. Capacitor architecture evolution
Technical innovation in capacitor processing continued
over the past 20 years in the industry, enabling DRAM
0038-1101/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2005.10.024
*
Corresponding author. Tel.: +33 43892 2049; fax: +33 43892 2122.
E-mail address: eric.gerritsen@philips.com (E. Gerritsen).
www.elsevier.com/locate/sse
Solid-State Electronics 49 (2005) 1767–1775

2. scaling into the sub-100 nm regime of today. Fig. 1 illus-
trates the successive architectures adopted. In the following
summary of DRAM capacitor technology since 1982, no
distinction is made between stand-alone and eDRAM as
both are driven by similar concerns like high capacitance,
high breakdown voltage and high capacitor density.
Between 1982 and 1985, DRAM density increased from
64 Kb to 1 Mb [2] using planar 2D-capacitors, from the
early PIS structure (poly–insulator–silicon: Fig. 1a) with
gate oxide dielectric to PIP capacitors (poly–insulator–
poly: Fig. 1b) which allow adjustment of dielectric thick-
ness and capacitance. The stacked capacitor, first proposed
in 1978 by Koyanagi et al. [3], was applied for industrial
1 Mb integration in 1985 [4], using a triple poly (Fig. 1c
and d).
From 1986 to 1990, DRAM density is driven from 1 to
16 Mb with design rules ranging from 0.8 to 0.4 lm. These
cells are produced with 3D-architectures and SiO2/Si3N4
dielectrics (ON/ONO). The capacitor surface is extended
in the third dimension.
From 1991 to 2000, DRAM evolution went from 64 Mb
towards the Gigabit era. Starting with a 0.4 lm CMOS
process using a stacked-capacitor cell, 1 Gb is demon-
strated with 0.25–0.16 lm CMOS. The third dimension is
no longer sufficient to maintain a large capacitance density
(in terms of fF/lm2
). Thus the Si3N4 content is optimized
to provide high capacitance and low leakage in 3D-PIP
architectures. Furthermore, the dielectric process is focused
on low thermal budget to ensure compatibility with CMOS
platforms.
Hemi-spherical grained polysilicon (HSG) is introduced
as bottom-electrode in the 0.18 and 0.15 lm nodes [5],
increasing the effective surface, as illustrated in Fig. 2.
Next efforts were focused on improving data-rate rather
than bit density and especially on embedded applications
with a pure Si3N4 dielectric.
From 2001 onwards, radical dielectric material changes
appear. Si3N4 is abandoned due to its high thermal budget.
MIS stacked-capacitors using high-k dielectrics and metal-
lic top electrodes are reported with 1 Gb chips using Ta2O5
[6] and 4 Gb using Al2O3 [7] in 0.10 lm technology. TiN is
the mainstream electrode material whereas alternatives,
like WN [8] or Ru [9], are being studied for higher work-
function and oxidation resistance.
DRAM then enters into the sub-100 nm technology
CMOS nodes, focusing on design and application issues.
New high-k dielectric materials, with low thermal budget,
are introduced to replace Ta2O5, along with the introduc-
tion of MIM capacitors.
Fig. 3 summarizes the evolution of DRAM density,
technology node, capacitor structure and dielectrics.
Fig. 1. DRAM architecture evolution from 1980 to 2005.
Fig. 2. HSG bottom electrode in 120 nm e-DRAM technology.
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
1980 1985 1990 1995 2000 2005
BITDENSITY
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
TECHNOLOGYNODE(µm)
HSG
MIMPIS MIS
electrode
structure PIP
year
Gb
Mb
TiN WN TaN Rupoly
dielectric SiO2 NO Si3N4 Ta2O5 Al2O3 HfO2 ZrO2
Fig. 3. Trend of DRAM production node, bit density, dielectrics and
electrode materials.
1768 E. Gerritsen et al. / Solid-State Electronics 49 (2005) 1767–1775

3. 3. Polysilicon electrodes/nitride dielectrics
The use of polysilicon as electrode material was
extended to 0.18 and 0.12 lm nodes by introducing hemi-
spherical grains (HSG, see Fig. 2). This allowed to more
than double the effective capacitor surface (Fig. 4).
A further increase of capacitance was obtained by intro-
ducing a pure nitride dielectric, without oxide (Fig. 5),
where leakage is reduced by operation at lower voltage
(Vdd from 1.8 to 1.2 V).
However, since our eDRAM uses stacked capacitors,
formed after transistor formation, the use of furnace based
HSG below 100 nm is limited by its high thermal budget
($650 °C) and the resulting degradation in performance
of the logic core process.
Other limitations of HSG below the 100 nm node are:
(1) Poly-depletion, with loss of capacitance giving an
increase of several A˚ ngstroms in SiO2 equivalent-
oxide-thickness (EOT).
(2) Formation of interfacial SiO2, further increasing
EOT.
(3) Non-uniformity of the dopant level at the bottom
and sidewall of the capacitor trench, giving additional
depletion and increasing polysilicon electrode resis-
tance. Poly-depletion, interfacial SiO2 and high-resis-
tivity can all be solved by introducing metallic
electrodes.
(4) The relatively thick layer of HSG gives a significant
reduction in effective surface area when shrinking
the capacitor cell (Fig. 6), thus counteracting the
increase due to the hemispherical grains.
Fig. 6 shows that HSG electrodes in the 90 nm node can
give over 30% area loss, whereas this is less than 5% for
thin TiN electrodes. Whereas it is hard to reduce the thick-
ness of HSG below 500 A˚ , metal electrodes can easily be
applied below 100 A˚ thickness (Fig. 7).
Similarly, the use of Si3N4 as a capacitor dielectric
beyond the 100 nm node is limited by its high-thermal
budget around 650 °C. In addition, its dielectric constant
is insufficient to meet the requirement on EOT which is
set at 18, 13 and 9 A˚ for the 90, 65 and 45 nm nodes,
respectively.
Fig. 4. Capacitance gain ($2.5·) achieved by introducing HSG. Note the
robustness of the process, as the four variations in doping level and film
thickness do not give significant changes.
Fig. 5. Capacitance gain (+20%) when replacing the oxide/nitride (ON)
dielectric by a pure nitride (NN) dielectric.
0.4
0.5
0.6
0.7
0.8
0.9
1
0 0.02 0.04 0.06 0.08 0.1
bottom electrode thickness (µm)
normalisedcapacitorsurface
180nm
120nm
90 nm
HSG
TiN
HSG @ 90nm
30% area loss
TiN @ 90nm
5% area loss
Fig. 6. Decrease of capacitor area due to thickness of bottom electrode for
180, 120 and 90 nm nodes. This counteracts the area increase of the
hemispherical grains.
Fig. 7. Embedded-DRAM cell with MIM capacitors, access transistors
and contacts.
E. Gerritsen et al. / Solid-State Electronics 49 (2005) 1767–1775 1769

4. Some high-k materials which have become available
offer much higher permittivity as well as higher bandgap
(Fig. 8) which improves leakage performance. This allows
a lower EOT, thus higher capacitance, at constant data
retention performance.
4. MIM development and perspectives
With the MIM capacitor cell established as the concept
of choice for our 90 and 65 nm e-DRAM technologies [10],
our development effort has been focused on:
• Choice of high-k dielectric and electrode materials: Al2O3
HfO2 and Ta2O5 as well as a Al2O3/Ta2O5 stack were
tested as the dielectric while different types of TiN were
evaluated for electrode materials.
• Choice of deposition technology: Metal organic CVD
(MO-CVD) and atomic layer deposition (ALD) have
been evaluated for dielectrics whereas PVD, CVD,
MO-CVD and ALD have been tested as electrodes.
4.1. High-k dielectrics
Fig. 8 and Table 1 give an overview of the most com-
monly applied high-k dielectrics. It shows that nature is
not generous on the trade-off between a high dielectric
constant (needed for high capacitor density) and a wide
bandgap (needed for low capacitor leakage).
The figure also indicates the potential of atomic
engineering by ALD, which is a very versatile technique
to generate mixtures or nano-laminates of oxides with a
more ideal behaviour.
This potential is further illustrated by the Ôrule of mix-
turesÕ in Fig. 9. This is a tentative model to estimate perfor-
mance of a mixture of high-k oxides, like that of TiO2
(narrow bandgap/high-k) and Al2O3 (wide bandgap/mod-
est-k).
4.1.1. Ta2O5—tantalum pentoxide
Ta2O5 has reached some maturity in DRAM processing
and is mostly deposited by MO-CVD, which is suitable for
mass production due to its reasonable deposition rate.
The electrical (capacitance/leakage) performance of the
deposited Ta2O5 film is critically dependent on a post-
deposition anneal in oxygen or ozone, required to lower
oxygen deficiency and carbon impurities in the film. An
aggressive anneal deteriorates interface quality and
increases capacitor leakage.
I(V) characteristics of a Ta2O5 MIM capacitor are
shown in Fig. 10 as a function of test temperature. A very
strong increase of capacitor leakage is observed when rais-
ing the temperature up to 125 °C, thus exceeding the spec-
ification of 10 fA/cell (@ ± À0.6 V).
Fig. 11 shows that the I–V curves measured for a 80 A˚
Ta2O5 MIM capacitor at 125 °C can be fitted to Schottky
emission (SE) behaviour at low electrical field and Poole–
Frenkel (PF) conduction at higher field.
SE is considered a conduction mechanism determined
by the electrode interface, whereas PF is important when
bulk defects dominate conduction.
The transition from SE to PF in Fig. 11 is observed
around 0.8 V, implying that leakage at our operating volt-
age of 0.6 V is dominated by Schottky emission and the
electrode interface.
The SIMS analysis in Fig. 12 of a 50 A˚ Ta2O5 layer on
TiN shows increased oxygen uptake of the metal electrode
with longer exposure to the oxidizing ambient during
Ta2O5 deposition.
3
7
11
15
0 20 40 60
dielectric constant k
Ebreakdown(MV/cm)
2
4
6
8
10
BandgapEg(eV)
Al2O3
TiO2
ZrO2HfO2
Ta2O5
SiO2
Si3N4
ideal
high-k
ALD
Fig. 8. Variation of bandgap and breakdown field with dielectric constant
for some common high-k dielectrics.
Table 1
Key parameters of high-k dielectrics evaluated
Dielecric
constant
Bandgap
(eV)
Barrier height
(towards TiN, eV)
Ebd
(MV/cm)
Ta2O5 25 4.4 1.7 3.5
Al2O3 9 8.8 3.7 7
HfO2 21 6 2.5 4
Fig. 9. The rule of mixtures applied to composites of Al2O3 and TiO2.
1770 E. Gerritsen et al. / Solid-State Electronics 49 (2005) 1767–1775

5. To reduce interface degradation of the bottom electrode
and resulting capacitor leakage, a high deposition rate is
therefore favourable. But the process margin remains
limited as step conformality of Ta2O5 deposition in the
capacitor trench degrades at higher deposition rate.
4.1.2. Al2O3—aluminium oxide
In comparing Al2O3 to Ta2O5, the first may offer only a
moderate dielectric constant, comparable to Si3N4 (Fig. 8),
but it is much less reactive than Ta2O5 towards metal elec-
trodes like TiN.
But most of all, Al2O3 offers a wide bandgap, much lar-
ger than both Ta2O5 and Si3N4, and comparable to that of
SiO2 (Fig. 8). Furthermore Al2O3 is in the amorphous state
1E-18
1E-17
1E-16
1E-15
1E-14
1E-13
1E-12
1E-11
1E-10
-2 -1 0 1 2
plate voltage (V)
leakagecurrent(A/cell)
T (°C)
125°C
25°C
100°C
75°C
50°C
bottom injectiontop injection
Fig. 10. Voltage/leakage characteristics of a 100 A˚ MO-CVD Ta2O5
MIM capacitor at temperatures from 25 to 125 °C.
0 0.2
PF
SE
Poole -
Frenkel
Schottky
emission
measured
JSE
T
2
.exp(v(q
3
V/ )/kT)
JPF
V.exp(v(q3V/ )/kT)
Voper
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
0.4 0.6 0.8 1 1.2
V plate (V)
leakagecurrent(A/cm2)
-
JSE
T (v ε ε
Voper
∼ ∼
Fig. 11. I–V dependence at positive bias (bottom injection) of a 80 A˚
Ta2O5 MIM capacitor with fitted curves for Schottky-emission and Poole–
Frenkel conduction mechanisms.
Depth (erosion time- sec)
10008006004002000
1e+2
1e+3
1e+4
50A
Ta2
O5
100A
TiN SiO2
deposition
@ 350˚C / 500sec
deposition
@ 400˚C / 60sec
Intensity
(counts)
Fig. 12. Oxygen uptake in TiN bottom electrode, as determined by SIMS,
for different deposition rates of the 50 A˚ Ta2O5 layer.
1E-18
1E-17
1E-16
1E-15
1E-14
1E-13
1E-12
1E-11
1E-10
-2 -1 0 1 2
Plate voltage (V)
Leakagecurrent(A/cell)
125˚C
25˚C
Fig. 13. I–V dependence at 25 and 125 °C for a MIM capacitor with 40 A˚
Al2O3 (17 A˚ EOT).
1
2
3
4
5
0 10 20 30 40 50 60 70
Dielectric thickness (Å)
Weibullslope
SiO2 MOS
Al2O3 MIM
Al2O3
Fig. 14. Weibull slope of Al2O3 (solid circle) and SiO2 (open squares) as
function of dielectric thickness.
E. Gerritsen et al. / Solid-State Electronics 49 (2005) 1767–1775 1771

6. after deposition and during subsequent processing. Other
high-k dielectrics, like HfO2 or ZrO2, suffer from crystallite
growth inducing increased surface roughness and leakage
paths along the grain boundaries. Al2O3 is often applied
in mixtures or laminates to prevent crystallisation of
higher-k dielectrics like HfO2 [11]. Finally Al2O3 is an
excellent diffusion barrier, notably for oxygen and hydro-
gen [12].
Al2O3 is deposited at around 400 °C by ALD, with
TMA as precursor and O3 as reactant, with no anneal
required.
Fig. 13 illustrates how Al2O3 offers low capacitor leak-
age with excellent temperature stability.
Fig. 14 shows that the thickness dependence of the
intrinsic Weibull slope for ALD-Al2O3, as taken from
TDDB curves, is in line with that of the highly reliable
SiO2.
According to percolation theory this implies that the
type and size of the defects related to dielectric breakdown
are similar for SiO2 and Al2O3.
The effect of Al2O3-thickness on leakage/capacitance
performance in Fig. 15 shows that tight thickness control
is required to prevent transition from voltage dependent
to direct tunnelling which occurs just below 40 A˚ leading
to a rapid rise of leakage current.
Atomic layer deposition of Al2O3 is able to meet this
requirement, offering control within $1 A˚ .
4.1.3. HfO2—hafnium oxide
The I(V) performance of Hafnium oxide HfO2 (with
k = 21 and Eg $ 6 eV) is compared to that of Al2O3 in
Fig. 16 and its temperature stability is shown in Fig. 17.
Fig. 16 shows HfO2 improves further on capacitor per-
formance as it combines the individual benefits of Ta2O5
(high k $ 25) and Al2O3 (high Eg $ 8.8 eV). Temperature
stability is similar to that of Al2O3.
Despite its superior electrical performance, the applica-
tion of HfO2 in capacitor manufacturing is still somewhat
retarded due to specific problems related to plasma etching
and thermal stability (recrystallisation) as well as to the
non-trivial integration of a new material in a CMOS
waferfab.
4.2. MIM capacitor electrodes
For MIM processing TiN remains a preferred electrode
material whereas alternatives like WN [8] or Ru [9] have
also been reported.
We have evaluated several techniques for the deposition
of TiN electrodes. Sputter deposition (PVD) lacks confor-
mality in the DRAM trenches. Standard CVD-deposition
based on TiCl4 is not ideal as it gives high-chlorine levels
which can only be reduced at high deposition temperatures
(>600 °C).
Metal organic (MO-CVD) type TiN, based on a
TDMAT precursor, contains large amounts ($10 at.%) of
residual carbon and oxygen.
Fig. 18A shows capacitor leakage behaviour when TiN
is deposited by either MO-CVD, using a TDMAT precur-
sor, or ALD, using a TiCl4 precursor, both at low temper-
ature (400 °C) and with NH3 as reactant. Fig. 18B shows
the corresponding capacitance values for these MIM
structures.
ALD-TiN is seen to give a 3 orders of magnitude
decrease of leakage current with a much tighter distribu-
tion, along with a 20% increase in capacitance compared
to TiN deposited by MO-CVD.
In Fig. 19 the application of ALD-TiN as bottom elec-
trode gives another 1.5 orders of magnitude in leakage
reduction.
Deposition of TiN by ALD offers superior purity and
stoichiometry without plasma damage. ALD-TiN enables
the application of high-k dielectrics at EOT values reduced
by several A˚ ngstroms, for the same level of capacitor
leakage.
In Figs. 20A and B the impurity profiles, as determined
by Auger spectroscopy, are compared for TiN deposited by
MO-CVD and ALD.
The deposition of MO-CVD TiN is normally followed
by an N2/H2-plasma treatment in order to reduce the
1E-16
1E-15
1E-14
1E-13
25 35 45 55
Al2
O3
thickness (A)
Leakagecurrent(A/cell)
Fig. 15. Capacitor leakage current (À1.8 V bias) of a MIM capacitor with
Al2O3 layer thickness varying from 35 to 50 A˚ .
1E-18
1E-17
1E-16
1E-15
1E-14
1E-13
1E-12
1E-11
1E-10
-2 -1 0 1 2
Plate Voltage (V)
CapacitorLeakage(A/cell)
75A HfO2
40A Al2O3
bottom injectiontop injection
25˚C
˚
˚
Fig. 16. I(V) curves for MIM capacitors with 40 A˚ Al2O3 (EOT 18 A˚ ) or
75 A˚ HfO2 (EOT 14 A˚ ).
1772 E. Gerritsen et al. / Solid-State Electronics 49 (2005) 1767–1775

7. amount of residual carbon and oxygen in the film. How-
ever, this plasma does not penetrate efficiently in the
DRAM trenches.
Therefore this densification and purification plasma
treatment was not applied to the blanket MO-CVD TiN
film in Fig. 20A. The remaining level of oxygen and carbon
could reach up to 30 at.% each.
For the ALD-TiN film the levels of oxygen, carbon and
chlorine are all below 1 at.%. Also more nitrogen is bonded
to the titanium (N/Ti = 1.2) which may favour a high
work-function of the electrode and lower capacitor
leakage.
Further evidence of the superior purity and interface
quality of ALD type TiN electrodes is presented in Figs.
21A and B and the corresponding TEM micrographs in
Figs. 22A and B. Both samples have MO-CVD TiN as
top electrode.
The bottom TiN electrode of Fig. 21A is deposited by
MO-CVD whereas that of Fig. 21B is deposited by ALD.
The interface of the MO-CVD type electrode is seen to
have suffered from severe intermixing of titanium and
nitrogen in the dielectric.
The improved interface integrity for the ALD-TiN inter-
face is further illustrated by the TEM cross-sections of
Figs. 22A and B.
These micrographs indicate that the interface between
dielectric and ALD bottom electrode is very smooth. This
is in contrast to the diffuse interface for the MO-CVD bot-
tom electrode in Fig. 22(A).
1E-18
1E-17
1E-16
1E-15
1E-14
1E-13
1E-12
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Vplate (V)
I(A/cell)
25˚C
125˚C
Fig. 17. I(V) temperature dependence of a MIM capacitor with 75 A˚ ALD-HfO2 dielectric.
Fig. 18A. Capacitor leakage for a TiN/Al2O3/TiN capacitor with TiN top
electrode deposited by MO-CVD and ALD bottom electrode is MO-CVD
TiN.
Fig. 18B. Capacitance values for the MIM structures of Fig. 18A.
Fig. 19. Capacitance/leakage performance for TiN/Al2O3/TiN capacitors
with TiN bottom electrode deposited by ALD and MO-CVD. Top
electrode is ALD-TiN.
E. Gerritsen et al. / Solid-State Electronics 49 (2005) 1767–1775 1773

8. Elemental microanalysis using EELS showed that the
voids observed in the dielectric layer of Fig. 22(A) contain
highly pressurized nitrogen gas.
Finally, the MIM architecture with high-k dielectrics
allows a limited capacitor height, giving less bitline cou-
pling, less parasitic capacitance and a lower aspect ratio
of the contacts (see Fig. 7).
Also the low electrode resistance of MIM capacitors
minimizes RC delay and offers fast read/write times
required for the high-speed designs of today.
5. Concluding remarks
Capacitor technology for eDRAM has flourished over
many process generations due to evolutionary innovations
like 3D-capacitors, hemispherical-silicon-grain electrodes
and (oxy)nitride dielectrics. Below the 100 nm node MIM
capacitors are adopted with novel high-k dielectrics.
For these nodes ALD deposition appears as an enabling
technology for both capacitor dielectrics and metal elec-
trodes. ALD offers great potential in the engineering of
novel composites of oxides with optimized capacitance/
leakage performance.
For many of these composites Al2O3 is a favourable
constituent. It provides chemical stability towards the elec-
trodes, stability against crystallite growth as well as a wide
bandgap, all improving capacitor leakage behaviour.
For 90 and 65 nm MIM capacitors the use of ALD-
Al2O3 as a high-k dielectric was found to give a favourable
compromise between capacitor performance and manu-
facturability. The use of ALD-TiN as electrode mate-
rial decreased capacitor leakage by several orders of
magnitude.
The industrial application of ALD still faces major chal-
lenges, for instance in terms of throughput. Processes with
optimised purge cycles [13], (semi-)batch processing [14]
and plasma-enhanced ALD [15] have been proposed to
meet these challenges.
To finish on a different note, we have recently reported
on a capacitor-less (1T/0C) DRAM cell [16], in order to
completely bypass the scaling limits of capacitor develop-
ment in the Gigabyte era.
Fig. 20B. Auger impurity spectra of ALD-TiN on SiO2.
Fig. 21A. STEM-EELS spectra across TiN/Ta2O5/TiN structure with
TDMAT based MO-CVD TiN bottom and top electrodes.
Fig. 21B. STEM-EELS spectra across a TiN/Ta2O5/TiN structure with a
TiCl4 based CVD-TiN bottom electrode. Top electrode by MO-CVD.Fig. 20A. Auger impurity spectra of MO-CVD TiN on SiO2. No post-
deposition densification/purification plasma is applied.
1774 E. Gerritsen et al. / Solid-State Electronics 49 (2005) 1767–1775

9. Acknowledgements
Jorge Regolini and Didier Dutartre are gratefully
acknowledged for the development of the oxynitride and
HSG modules described in Section 3. ALD development
was supported by Franc¸ois Martin at CEA-LETI, Greno-
ble. Vincent Huard and Frederic Monsieur are acknowl-
edged for extensive reliability testing of MIM capacitors.
Part of this work was realized in the framework of Euro-
pean Eureka program MEDEA+ T-126 (BLUEBERRIES)
on embedded memories.
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Fig. 22. TEM micrograph of the TiN/Ta2O5/TiN structures of Figs. 21A and B. Top electrode is to the right.
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