1. U O
D C
U R II
Deposition of n+ poly-Si thin films
Lars Kristian Henriksen
A paper submitted in fulfilment of the requirements
for the course
KJM3020.
20 credits
Spring, 2016
2.
3. Abstract
A method for depositing highly phosphorus doped silicon ([P]⇠ 5 ⇥ 1019
cm 3
) by sputtering, pro-
ducing poly-crystalline and conductive thin films without the use of a substrate bias is explained.
The samples were characterized by four point measurements, Hall e ect measurement, atomic force
microscopy, x-ray di raction and secondary ion mass spectrometry. It is shown that samples etched
by reactive ion etch prior to sputter deposition at 200 C for 30 minutes and subsequent furnace
annealing at 1100 C for 30 minutes produces 270 nm thick films with a sheet resistivity as low
as ⇠ 2.8 ⇥ 10 2
⌦ cm and a carrier density and mobility of ⇠ 2.0 ⇥ 1019
cm 3
and ⇠ 12 cm2
/ Vs,
respectively. X-ray di raction patterns indicated both Si (111) and (220) planes, and atomic force
microscopy statistical calculations found the surface to have a root mean square average height of
⇠ 1 nm.
i
6. 1
I
Fall 2015. Paris. Top politicians from 195 countries meet to discuss the future of the planet [1].
After Copenhagen Climate Change Conference in 2009 the world doubted that Paris would be a
game changer and few believed that a climate deal would be struck. But 12/12/2015 the agreement
was signed, making it the first-ever legally binding climate deal. The agreement spring into action
in 2020 and it is believed that it will help us reach the much talked of two degree goal [2]. Norway
proposed a 40% reduction in greenhouse gases by 2030 [3] and through this indirectly committed
itself to become a leading figure in the green technology revolution. To reach the goals set forth in
Paris, new technology is required, and first and foremost green technology.
An important aspect to consider when finding new ways of harvesting energy is the environmen-
tal aspect of both production and use. Solar cells made from potentially toxic materials such as GaAs
and CdTe are not uncommon [4] and poses a potential risk to both humans during production of the
units, as well as the environment, during production and the end of life disposal. Making solar cells
of the future greener should therefore also imply making them environmentally friendly and non
toxic.
This project is part of a bigger project with an ultimate goal of creating a tandem Si-Cu2O solar
cell capable of capturing a larger portion of the incoming sun radiation, enabling higher e ciencies,
than the single junction silicon solar cells of today, while sticking to low cost materials. As silicon
and cuprous oxide are both more enviromentally friendly than other solar cell setups [4] and highly
abundant in the earth crust these are highly attractive materials to investigate.
One of the challenges of this new tandem structure is creating a tunneling junction between the
silicon cell and the cuprous oxide cell to enable electron transport between the two. To achieve this
quantum e ect a well defined p+
-n+
junction is needed and in this paper a method for thin film
deposition of highly phosphorus doped ([P]⇠ 5 ⇥ 1019
cm 3
) silicon targets onto a quartz substrate
is explained in an e ort to facilitate a safe and scalable method for making highly doped silicon thin
films.
The original project description read
The purpose of this project is to deposit a thin film n+
- Si-layer onto a silicon substrate
by the use of e-beam evaporation and sputter deposition and to characterize this thin film.
The goal is to make a thin film with high charge carrier mobility and concentration. The
thin film should also be a suitable substrate for further Cu2O deposition. The task is part
of a bigger project of making a tandem solar cell combining a conventional silicon solar
cell with a Cu2O cell.
This description was largely followed but a slight modification was imposed early in the project
making sure to keep the time frame set forth; instead of using a silicon substrate quartz would be
used to simplify sample characterization. Surface characterization to specifically investigate the
possibility of further growth of Cu2O was not undertaken.
1
7. 2
T
2.1 Silicon
Silicon is a group IV semiconductor and is often referred to as an elemental semiconductor because
it is composed of one species of atoms. Today silicon is by far the most common semi conductor
material in rectifiers, transistors and integrated circuits as well as in solar cells due to its high
abundance, relatively low cost and superior properties.
(a) Diamond crystal structure unit cell. Source: http:
//hyperphysics.phy-astr.gsu.edu/hbase/solids/sili2.html
0
1
2
0
1
2
0
1
2
0
1
2
0
1
4
3
4
3
4
1
4
(b) Atomic positions in the cubic cell where points at
0 and
1
2
are on the fcc lattice. The points
1
4
and
3
4
are on a similar lattice displacement along the body
diagonal by one-fourth of its length [5].
Figure 2.1: The silicon unit cell crystal in 3D and 2D.
Silicon in a pure and perfect crystalline form takes on a diamond crystal structure, an fcc lattice
with a two atoms basis. In this structure all Si-atoms are bound to four other Si-atoms by directional
covalent bonding as shown in figure 2.1a.
This produces a unit cell consisting of 8 atoms, four of which are completely enclosed in the unit
cell, plus four that is on the fcc lattice as shown in figure 2.1b. According to Kittel [5] the lattice
constant for silicon is a = 5.430, where a is the edge of the conventional cubic cell.
Introduction of impurities in the silicon crystal, substituting the Si atoms with group III or V
elements such as boron (III,trivalent) or phosphorous (V,pentavalent), introduce a change in charac-
teristics and is called doping. This is due to the di erence in the number of silicon valence electrons
and the valence electrons of the introduced impurity.
Boron, an acceptor, has one less valence electron and a mobile positive charge will be introduced
to the lattice, often referred to as a hole. Enough impurities introduces a new energy band in the
silicon band gap close to the valence minimum band energy level (VBM). Phosphorous, a donor,
will introduce a mobile negative charge, electron, to the lattice and a new energy band close to the
conduction band minimum energy level (CBM). By introducing new energy bands close to the VBM
or CBM, less energy is needed to excite electrons from the valence band or to the conduction band,
enabling conduction.
2
8. CHAPTER 2. THEORY 2.2. DOPING
Figure 2.2: The pn - junction characteristics. Source:
https://upload.wikimedia.org/wikipedia/commons/f/fa/
Pn-junction-equilibrium-graphs.png
Semiconductors with
an excess of negatively
charged carriers are called
n-type semiconductors; an
excess of positively charged
carriers are called p-type.
Combining bulk p- and n-
type material gives rise
to a p-n junction. As
shown in figure 2.2 mo-
bile charge carriers dif-
fuse over the junction to
cancel out charge and by
doing this creates a re-
gion around the junction
with stationary charges
which sets up an elec-
tric field. At equilibrium
this electric field is great
enough to stop any fur-
ther di usion of free car-
riers and a depletion re-
gion is formed.
This region acts as a
barrier for majority car-
riers (electrons on n-side
and holes on p-side), and
a low resistance path for
minority minority carri-
ers. By introducing a
forward or reverse bias
over the junction the de-
pletion region can be ma-
nipulated, but it can also
be manipulated by dop-
ing the samples; highly
doped samples will have
a smaller depletion zone
as more fixed charge are
concentrated close to the junction. Oppositely, lightly doped samples experience a deep depletion
zone as fixed charge is less dense.
With a small enough depletion zone a quantum e ect called tunneling is more probable. Elec-
trons in the p-side valence band tunnel to the n-side conduction band without experiencing the
barrier at the p-n junction since the probability of electron tunneling through an energy barrier
increase exponentially with decreasing tunneling distance.
2.2 Doping
Doping semi-conducting materials is today a widely used technology with almost unlimited applica-
tions. According to Wikipedia [6], the history of doped semi-conductors may be traced back to 1885
when it was first observed that the properties of these materials were due to the impurities within
the material itself, but it was not until the mid 40’s that a process was formally developed by John
Robert Woodyard.
One of the first groups to report on incorporating pentavalent (elements with five valence elec-
trons) and trivalent impurities (elements with three valence electrons) into a tetrahedral amorphous
semiconductor (a-Si) was Spear and Comber [7] in 1975 by chemically reacting silane gas (SiH4)
mixed with phosphine gas (PH3) in a process they called "electrode-less glow discharge", known
today as Plasma Enhanced Chemical Vapor Deposition (PECVD). Spear and Comber [7] state that
3
9. CHAPTER 2. THEORY 2.3. CRYSTALLIZATION
...the e ect of the pentavalent impurity has been to increase the conductivity of a-Si
by seven orders of magnitude...
This process have been perfected over many years and with modern equipment, groups like Ku-
mar et al. [8] produce samples with carrier concentrations close to 4 ⇥ 1020
using PECVD.
Producing highly doped silicon thin film can be accomplished in a number of ways. One partic-
ularly promising method is sputtering, this due to the reduced temperature needed for deposition,
elimination of toxic gases such as PH3 and ability to pre-dope the Si-targets [9].
Sputtering of highly doped Si is far less discussed in literature than PECVD, but both Jun et al.
[10] and Wang et al. [11] has had success with the method producing films with mobility and carrier
concentrations of 1.2 cm2
/ V s and 6.5 ⇥ 1017
cm 3
(n-type), respectively. For further discussion on
this topic refer to section 3.2.2.
2.3 Crystallization
Due to the fact that sputtering Si onto a substrate produces amorphous thin-films, a post-deposition
crystallization process is required to achieve the poly-Si films needed for device application since the
conductivity and resistivity, are highly dependent on crystallinity. Understanding the crystalliza-
tion processes is therefore crucial.
This project utilizes solid phase crystallization due to the negative e ects liquid phase crystal-
lization would have on the p+
- n+
transition layer. Keeping doping levels intact throughout the
crystallization process is important to obtain the desired characteristics.
When crystallizing a Si-film there are mainly two processes a ecting the outcome: nucleation
and growth [12–15]. As Spinella et al. [14] states in their paper, growth rate highly depends on
available nuclei in the sample after deposition, and that the properties of the polycrystalline Si
layers depend on the properties of the as-deposited a-Si layers. Their results indicates that favor-
able nucleation sites occur during deposition and in an e ort to control these nucleation sites a pre
deposition reactive ion etch is included in this project.
In addition to the nuclei dependence, crystallization rate has a strong dependence on the anneal-
ing temperatures as the activation energy for nucleating silicon crystals has a high value of 3.9 eV
[16]. Typical crystallization parameters are 600 C for 20h [10], while it is 750 C for 2 minutes [11]
(rf magnetron sputtered films with and without substrate bias) up to 900 C-1100 C for 3 minutes
[17] in the case of rapid thermal processing. This shows that the crystallization rate of sputtered
a-Si increases rapidly with increasing temperature up to about 1100 C-1200 C.
4
10. 3
T
3.1 Pre-deposition Techniques
3.1.1 Reactive Ion Etch
In reactive ion etching (RIE), often referred to as dry etching or plasma etching, ionized atoms are
accelerated towards a sample under an applied negative bias. In non-conduction materials such as
silicon a radio frequency (rf) potential is applied to maintain the bias [18].
RIE may use chemically reactive plasma to attack the sample, chemically removing the top layer
of the sample atom by atom. It is also possible to increase the power and use this as a physical etch
by sputtering of the surface (see 3.2.2);it is this physical method that is being used in this project.
The steps in RIE are adsorption, reaction and desorption. The amount removed depends on etching
time, power and reaction gas and is hence controllable as shown by Abe et al. [19].
3.2 Deposition Techniques
There are a vast number of deposition techniques used in thin film production today. They are
usually classified as chemical vapor deposition (CVD) or physical vapor deposition (PVD) and di er
in that CVD utilizes a chemical reaction to obtain film growth while PVD does not. Instead PVD
vaporizes a target material by either a thermal (e-beam) or athermal (sputter) process.
CVD and especially plasma-enhanced CVD (PEVD) is a widely used technique in preparation of
silicon thin films [8, 20–23]. This technique utilize the chemical reaction of multiple gases to grow
the film, such as PH3 and SiH4 to produce highly doped silicon films as described by Kumar et al. [8].
This technique produces high quality films but does come at a price as the phosphine gas is highly
toxic [24].
With this in mind, the preferred techniques in this project does not involve CVD’s. Both electron
beam assisted PVD (EB-PVD) and sputtering are classified as PVD techniques and the following
discussion will mainly concern these.
3.2.1 Electron Beam Assisted Physical Vapor Deposition
A quick historical review
The predecessor to this technique is thermal evaporation of solids first described by Faraday in the
1850’s. Faraday [25] used thermal energy to either evaporate or sublimate the target material. The
road onward is described in detail by Anders [26] covering the history of cathodic arc coating.
Electron Beam Assisted Physical Vapor Deposition Theory
In Electron Beam Assisted Physical Vapor Deposition (EB-PVD) a high energy electron beam is
produced and subsequently directed at the target material to induce the vaporization. In this set-up
the source producing the electron and target acts as the cathode and anode, respectively, where the
former is e ectively a filament exposed to a high voltage (6-40 kV), in turn ejecting a high density
5
11. CHAPTER 3. TECHNIQUES 3.2. DEPOSITION TECHNIQUES
flow of electrons. These electrons are then deflected and directed at the target material by an applied
electric and magnetic field.
The chamber where this process occurs should be held at high vacuum as this will increase the
mean free path of the vaporized atom, reducing the gas-to-gas collisions en route to the substrate
and increasing the deposition rate and uniformity.
As Arunkumar et al. [27] further states and concludes, the EB-PVD is a process involving several
crucial steps and the deposition process depend on the applied voltage, vacuum pressure and electron
beam diameter incident on the target.
3.2.2 Sputtering
Sputtering is an attractive technique for depositing Si films, compared to CVD, due to the re-
duced temperature needed for deposition, elimination of toxic gases such as PH3, controlling the
H2-concentration in the deposited film and ability to pre-dope the Si-targets [9]. It is also easily
scalable and ’industry friendly’.
A quick historical review
Sputtering was discovered in 1852 and 1858, independently, by William Robert Grove and Julius
Plücker, respectively [28]. The practical use of sputtering may be traced all the way back to 1877
[29] when it was used to coat mirrors.
For many years this technique was used, but not well understood. Other less complicated and
better understood evaporation techniques emerged and research in the sputtering technique halted.
It was not until the late 50’s that the demand for higher quality thin films of a variety of materials
again made sputtering an area of interest for scientists [28].
Sputtering theory
The sputtering method involves physical vaporization of atoms from a target surface by bombarding
it with ionized gas atoms in vacuum. In this project Ar gas is used. The ions are accelerated in an
electric field and hit the target surface, breaking loose atoms from the target which are then free to
move towards, and hit, the substrate.
In the process of breaking o atoms from the target, the atoms gain momentum. The momentum
transfer theory is based on the work done by Guntherschulze in the 20’s and 30’s and Wehner et al.
in the 50’s and 60’s [30] and is the basis for understanding the sputtering process.
In his book Mattox [30] lists the e ect explained by the momentum transfer theory. Shortened
to some degree, Mattox states that: sputter yield ("ratio of atoms sputtered to the numbers of high
incident particles") depends on the energy, mass and angle-of-incident of the bombarding particle.
Below a certain energy sputtering does not occurand at high energies the sputtering yield is low
because the ions lose much of their energy far below the surface of the target. When sputtering
polycrystalline material, some crystallographic planes sputters faster than others.
Di erent methods of sputtering exist, the most common being dc (direct current) sputtering and
the rf (radio frequency) sputtering. In the dc system the front side of a cathode is covered with the
target material to be deposited and the substrate is placed on an anode. The sputtering chamber
is filled with sputtering gas, and the glow discharge is maintained by the application of dc voltage
between the electrodes. The Ar+
ions generated are accelerated at the cathode and sputters the
target [31]. To maintain the glow discharge a metal target is needed to avoid a immediate buildup
of a surface charge on the front side of the target.
Substituting the metal with an insulator would not work with the dc sputtering system. In the
case of sputtering insulating material, the rf sputtering system is used where the glow discharge is
maintained by applying an rf voltage to the insulating target.
The system used for this project is the rf magnetron sputtering system where a cylindrical mag-
netic field is applied to the target. The magnetic field traps electrons in the vicinity of the sputtering
gas, increasing the collision rate between electrons and the sputtering gas, increasing the plasma
density and sputtering yield [31].
Sputtering of highly doped silicon
Groups first reporting on sputtered doped Si films used impurity chips attached to Si wafers, con-
trolling the doping concentration by varying the area ratio of the impurity chip to Si wafer [32, 33].
6
12. CHAPTER 3. TECHNIQUES 3.3. POST DEPOSITION TECHNIQUES
As highly pre-doped Si wafers became available the preferred technique shifted from co-sputtering
to using the highly doped target, giving better control of the majority carrier concentration in the
deposited film.
This technique was used by Fenske and Gorka [34] to prepare phosphorus doped Si films by
sputtering of 1-2 m⌦ cm P-doped target producing Si films with carrier concentrations of 7 9 ⇥
1019
cm 3
and mobilities of 50 cm2
/Vs.
Experimental results on films produced by sputtering of highly B and P doped Si-targets, an-
nealed by RTA at 1100 C, shows a carrier concentration of 1.6 ⇥ 1019
cm 3
in the B-doped samples,
approximately one order of magnitude higher than the P-doped samples [17]. Wang et al. [17] shown
the doping e ciency of B and P atoms to be 28% and 0.62%, respectively.
3.3 Post Deposition Techniques
3.3.1 Rapid Thermal Processing
Rapid thermal processing (RTP) is a widely used annealing technique in semiconductor technology
ever since IBM came up with the technique in the late 60’s [35]. With RTP the wafer is heated quickly
at atmospheric or low pressure [36]. Heat is provided by halogen lamps placed in close proximity
to the wafer. The lamps heat the wafer to 1100-1200 C on a timescale of several seconds or less.
The wafer is placed in a graphite holder, which in turn is placed on four quartz spikes, keeping
the contact area between the graphite wafer-holder and the surrounding equipment to a minimum.
A temperature measurement system is placed in a control loop, measuring the wafer temperature
directly.
RTP has many applications including activation of dopants, densification of the deposited film
along with solid phase crystallization (SPC). Traditionally furnace annealing (3.3.2) was used for
SPC but RTA has show to be a well suited substitute and even though higher temperatures are
needed in this process [17, 37] the total thermal budget are orders of magnitude smaller because of
the short annealing duration.
3.3.2 Furnace Annealing
Furnace annealing is a common technique in semiconductor device fabrication. This type of heat
treatment produces much of the same result as with RTP such as dopant activation, film desification
and solid phase crystallization, among other.
Annealing duration in furnaces are usually long such as in Jun et al. [10] paper where annealing
times of 20 hours are used. This is usually not problematic, but at high temperatures (>1000 C)
dopants may start to di use and a well defined p-n junctions may not be achieved.
A gas flow system is usually part of a furnace annealing set-up enabling oxidation steps, or the
opposite; flushing the chamber with gases to suppress oxygen to ensure that oxidation does not take
place.
3.4 Characterization Techniques
3.4.1 4-point probe
The four-point probe is widely used for resistivity measurement in semiconductors. It is an absolute
measurement with no need of calibrated standards and is therefore often used to provide standards
for other resistivity measurements [38].
Weimer [39] first proposed the four-point probe in 1916 as a tool to measure the earth resistivity,
and in 1954 Valdes [40] adopted the technique for resistivity measurements in semiconductor wafers.
The spacing between the four probes are usually identical as shown in figure 3.1, and it is this
assumption that Schroder [38] uses to derive the following expression for measuring resistivity
⇢ = 4.532
U
I
t (3.1)
where ⇢, U, I and t is resistivity, voltage, current and wafer thickness, respectively. The correction
factor 4.531 is valid for t s/2 where s is the probe spacing; the film thickness needs to be less than
the probe spacing, which in this work always applies with film thickness 300 nm.
7
13. CHAPTER 3. TECHNIQUES 3.4. CHARACTERIZATION TECHNIQUES
s s s
⇠
VI
I
Figure 3.1: Four-point probe schematics
The measurement is done by applying a current I over the outside probes, then measuring the
voltage over the two interior probes.
3.4.2 Hall e ect measurement
Hall e ect measurements plays a big part in semiconductor physics because of its ability to measure
resistivity, carrier concentration and mobility. All these three factors are discussed in detail later
in this section, but they are all, to some degree, found by utilizing the Hall e ect.
B
I
VH
1
2
4
3
qv
F
E
Figure 3.2: Hall e ect schematics with a I13 V24 van der Pauw setup on a n-type semiconductor.
The hall e ect was discovered in 1879 by Hall when he was investigating the forces acting on a
conductor carrying a current in a magnetic field [41]
Hall found that a magnetic field applied to a conductor perpendicular to the current
flow direction produces an electric field perpendicular to the magnetic field and the cur-
rent
In semiconductor physics this translates to a magnetic field perpendicular to the charge carrier
direction of travel. The force on the carriers is given by
F = q(E + v ⇥ B) (3.2)
and as shown in figure 3.2 this results in a accumulation of carriers, setting up an electric field
with magnitude proportional to the magnetic field as well as the carrier velocity by
Ey = Bzvx (3.3)
8
14. CHAPTER 3. TECHNIQUES 3.4. CHARACTERIZATION TECHNIQUES
often referred to as EH, Hall field. From this induced field it is possible to derive the type of
charge carrier (n- or p-type), carrier concentration and mobility. The electrical current density may
be expressed as
J = nqvx (3.4)
where n is the number of charge carriers, q the electron charge and vx the carrier velocity as used
in equation 3.2. The current is then given as
Ix = Jx!t (3.5)
where !t is the cross-sectional area of the semiconductor. The Hall voltage VH (V24 ref fig 3.2),
measurable as the the potential di erence across the sample, is related to the Hall field by
VH =
!Z
0
Ey dy = Ey` (3.6)
Combining equation 3.3, 3.5 and 3.6
VH =
✓
1
nq
◆
IxBz
t
(3.7)
where the first term is called the Hall coe cient
RH =
1
nq
(3.8)
If this value is negative, the charge carriers are negative, and if positive the charge carriers are
positive. In practice, the polarity of VH determines the sign of the charge carriers [42].
Knowing the Hall voltage at a specific current and magnetic field yields a value for the carrier
concentration through
n =
1
qRH
=
IxBz
qtVH
(3.9)
and as all the quantities on the right hand side of this equation can be measured carrier concentra-
tions are easily derived by this method.
3.4.3 Resistivity
Resistivity in thin films with uniform thicknesses are often referred to as sheet resistivity. If a
measurement of resistance R is made, the sheet resistivity ⇢ can be calculated by [43]
⇢ =
R!t
L
=
V13/Ix
L/!t
(3.10)
where L is the length between contacts (1-3 ref fig 3.2).
Resistivity is in itself an important property as it contributes to the device series resistance,
capacitance, threshold voltage among others [38].
The resistivity depends on the free electron and hole densities n and p and their respective mo-
bilities µn and µp through the relationship
⇢ =
1
q (nµn + pµp)
(3.11)
9
15. CHAPTER 3. TECHNIQUES 3.4. CHARACTERIZATION TECHNIQUES
In extrinsic materials where the majority carrier density is many order of magnitude higher than
the minority carrier density, equation 3.11 can be written
⇢ =
1
qnµn
for n-type material (3.12)
⇢ =
1
qpµp
for p-type material (3.13)
These equations are used to calculate the mobility in the semiconductor.
3.4.4 Van der Pauw
This setup is commonly used in Hall e ect measurements to measure resistivity, carrier concentra-
tion, and carrier mobility (often referred to as Hall mobility). The sample is placed on an isolating
sample holder and set up as shown in figure 3.3 by soldering conducting wires to each corner of a
sample. Arbitrary shapes may also be used as explained by Schroder [38], but as the calculations
are a lot easier with symmetrical shapes, square samples are most common when using the Van der
Pauw method.
I V
2 3
1 4
Figure 3.3: Van der Pauw schematics, depicting a I12-V34 set-up.
As shown in figure 3.3 the four contacts are given numbers 1,2,3 and 4. Current is sent between
two of the contact points and I12 equals current sent between contact point 1 and 2. The measured
voltage is denoted in the same way over the contacts not used to pass current, such as V34. The
resulting resistance in this set-up, governed by Ohms law, is denoted as R12 34.
By measuring all contacts, two characteristic resistances RA and RB are found, an average of the
four possible geometric combinations
RA =
1
4
(R12 34 + R21 34 + R34 12 + R43 12)
RB =
1
4
(R23 41 + R32 41 + R41 23 + R14 23)
From Schroder [38], equation (1.25) describes the resistivity:
⇢ =
⇡
ln(2)
t
RA + RB
2
F (3.14)
where t and F are film thickness and a function of the ratio Rr = RA/RB, respectively. For a sym-
metrical sample, such as a perfect square, Rr = 1 and F = 1 allowing equation (3.14) to be simplified
to
⇢ = 4.532tRA (3.15)
and is the same as used in four point measurements described in section 3.4.1.
To measure carrier concentration, mobility and type(n- or p-type) a magnetic field is applied
perpendicular to the sample. Calculations on mobility, carrier concentration, hall coe cient and
type of charge carrier are described in section 3.4.2.
10
16. CHAPTER 3. TECHNIQUES 3.4. CHARACTERIZATION TECHNIQUES
3.4.5 Atomic Force Microscopy
Atomic force microscopy was first described in 1986 by Binnig et al. [44] where they state that
...this level of sensitivity clearly penetrates the regime of inter atomic forces between
single atoms and opens the door to a variety of applications. The atomic force microscope
(AFM) is a new tool designed to exploit this level of sensitivity.
The method enabled scientists to view surface structures in a new and more detailed way. After
1986 there has been a lot of improvements on the AFM and today we can achieve high resolution,
nano-scale pictures.
Sample
Laser
Cantilever
Photo
detector
Figure 3.4: Atomic Force Microscope schematics
To achieve this super detailed view
of surfaces, the weak forces between the
sample surface and a very sensitive can-
tilever is utilized.
In tapping mode the tip, or probe,
is driven to oscillate at or near its res-
onance frequency. As the tip closes in
on the surface the forces between the
tip and the surface causes the amplitude
of the oscillating tip to change. This
change, detected by the position sensi-
tive photo detector, is sent to the piezo-
ceramic servo which raises or lowers the
probe to maintain a certain height over
the surface. The movement data of the
servo is used to produce a three dimensional topographical mapping of the surface.
3.4.6 X-ray di raction
X-rays was first discovered in 1895 and in 1912 Max von Laue found that crystalline substances act as
three dimensional gratings for x-rays with wavelengths similar to the crystal lattice parameters [45].
Figure 3.5: Energy transitions resulting
in the characteristic CuK’s. Source: https:
//upload.wikimedia.org/wikipedia/commons/thumb/
d/d8/Copper_K_Rontgen.png/220px-Copper_K_
Rontgen.png
This enabled scientists to probe crystal
structures in a new and revolutionary
way and has become a common tech-
nique for the study of crystal structures
and atomic spacing.
The x-rays are produced by bombard-
ing a metal with a beam of electrons, ion-
izing 1s electrons from the target atom.
As electrons from the 2p and 3p levels
drop down to fill these vacancies, x-rays
are released and form characteristic x-
ray spectra, the most common being K↵
(2p ! 1s) and K (3p ! 1s)[46].
Copper is a common metal in pro-
ducing x-rays for x-ray di raction (XRD)
characterization and the characteristic
wavelength used in XRD is
CuK↵ = 1.5418 Å
K and other less intense wave-
lengths are removed by a monochroma-
tor. K↵ consists of K↵1 and K↵2 where
K↵1 has a slightly shorter wavelength
and twice the intensity as K↵2 [45]. If
K↵1 and K↵2 wavelengths are far enough apart in energy to produce a clear reflection it is possible
to filter out K↵2 as well.
11
17. CHAPTER 3. TECHNIQUES 3.4. CHARACTERIZATION TECHNIQUES
Bragg’s Law
By using Bragg’s law it is possible to determine the crystal lattice dimensions and which crystal
planes are present in the sample. A vast number of reflection patterns are documented and the use
of databases are needed when deciding which planes are present in a sample.
Bragg’s law is a universal law concerning the behavior of waves in crystals and other solids.
Incoming x-rays with a certain wavelength penetrate the first atomic layer and interact and scatter
o atoms in the second layer as shown in figure 3.6.
Figure 3.6: Bragg reflection schematics with two incoming waves at di raction. Source:http:
//hyperphysics.phy-astr.gsu.edu/hbase/quantum/imgqua/bragglaw.gif
The distance d denotes the spacing between the first and second layer and the distance 2d sin ✓
is the total extra distance traveled by the wave reflected o the second layer compared to the wave
reflected o the first layer, and if this equals n , n being an integer, the two waves experience con-
structive interference. A peak in intensity is observed and Bragg’s law, n = 2d sin ✓ is fulfilled.
Every part of this equation, except for d, can be found through an experimental setup and solving
for d produces
d =
n
2 sin ✓
(3.16)
Figure 3.7: X-ray di raction schemat-
ics. Source: http://chemwiki.ucdavis.edu/
@api/deki/files/232/=xrd.png?revision=
1&size=bestfit&width=323&height=237
Because of the n dependency, incoming waves
with close to the lattice parameter is desirable
in solid state characterization. As a result us-
ing x-rays produced by copper with a characteris-
tic wavelength CuK↵ = 1.5418 Å (see 3.4.6) when
characterizing silicon with a crystal lattice con-
stant of 5.431 Å (in diamond FCC crystal) works
well as these values are within the same order of
magnitude.
As shown in figure 3.7 an x-ray source sends a
beam directly at the sample and a detector is set up
to collect the reflected rays. In a typical ✓/2✓-scan
the sample holder rotates at an angle ✓ while the
detector rotates at an angle of 2✓ over a scan inter-
val. Intensities are logged at each measurement
point and yields a plot such as figure 5.11.
3.4.7 Secondary Ion Mass Spectroscopy
Secondary Ion Mass Spectroscopy (SIMS) is one of the most powerful analytical techniques for semi-
conductor characterization. After it was developed in early 60’s it has become a leading characteri-
zation method capable of detecting all elements as well as isotopes and molecular species.
The basis of SIMS is the removal of material from the sample surface by sputtering and subse-
quently analyzing the ejected material. Only about 1% of the total ejected material are positively
12
18. CHAPTER 3. TECHNIQUES 3.4. CHARACTERIZATION TECHNIQUES
Figure 3.8: Secondary ion mass spectroscopy schematics.
Schroder [47]
or negatively charged and SIMS
therefore uses the mass/charge
ratio of the ions to analyze
the sample. This is sometimes
problematic as various com-
plex molecules form during the
sputtering process which may
be confused for natural ele-
ments.
Depth profiling is another
strength of SIMS. Plotting the
intensity of a selected mass
versus sputtering time and
converting this to density ver-
sus depth is possible when
the primary ion beam current,
sputter yield, ionization e -
ciency, atomic fraction to be
analyzed and an instrumental
factor is known. Some of these
factors may be hard to find and experimental standards are commonly used Schroder [47].
13
19. 4
E
The experimental part of this project was divided into three phases, one initial and two main phases.
The final phase builds on the results found in the previous two phases.
General procedures
Fused silica substrates were used in all depositions. A 3" quartz wafer was laser cut into 1x1 cm2
pieces and cleaned in acetone, isopropanol and water for 2, 10 and 5 minutes, respectively, dried o
by N2 gas and stored in an airtight plastic bag for later use.
4.1 Phase I - Initial investigations
Phase one was the initial phase where the goal was to find deposition parameters which could pro-
duce the desired film quality. A fairly unsystematic approach was used producing a total of five pairs
of samples.
4.1.1 Deposition
Electron Beam Physical Vapor Deposition
300 n of silicon was deposited by electron beam physical vapor deposition (EB-PVD) using an Evo-
Vac chamber from Ångstrom Engineering. The target material was highly phosphorus doped ([P]⇠
5 ⇥ 1019
cm 3
) silicon. No substrate heating was applied during the first deposition; the second
deposition was done with a substrate temperature of 300 C. Initial chamber pressure at deposi-
tion initiation was measured to be 2.0 ⇥ 10 6
Torr in both cases, decreasing during deposition to
8.5 ⇥ 10 7
Torr and 9.2 ⇥ 10 7
Torr in the low and high temperature run, respectively.
Sputtering
Three sets of samples were sputter deposited at di erent temperatures; room temperature, 300 C
and 600 C in a Semicore Triaxis DC/RF Magnetron Sputter with each set containing two samples
to facilitate secondary ion mass spectrometry (SIMS) measurements. A phosphorus-doped target
material was used and all depositions were initiated at a chamber pressure below 2.0 ⇥ 10 6
Torr.
An argon gas flow of 50 SCCM was introduced into the chamber and plasma was ignited resulting
in a deposition pressure of 7.1 mTorr. A ten minute pre-sputtering period was included to clean the
target surface.
4.1.2 Characterization
Four point measurement
The sheet resistance of all samples was measured using a Jandel KM3-AR four point probe unit in
high resistivity mode and auto ranging was used in order to find applicable current values.
14
20. CHAPTER 4. EXPERIMENTAL 4.2. PHASE II - HEAT TREATMENT
X-ray di raction
One sample from phase I was characterized by X-ray di raction to extract structural information. A
Bruker AXS D8 Discover unit was used in ✓/2✓-scan mode from 2✓ = 20 to 2✓ = 90 with increments
of 0.01 at a scan rate of 0.1 seconds per increment.
4.2 Phase II - Heat treatment
The idea of phase two was to broaden the angle of view and systematically test the techniques found
to work in literature. Although a lot of the literature was based on plasma enhanced chemical
vapor deposition (PECVD), annealing temperature is usually found to be the determining factor in
crystallization of a-Si and this parameter was varied as shown in table 4.1. Annealing temperatures
investigated in the literature range from 600 C in a traditional furnace setup [10] to 1100 C in a
typical rapid thermal processing (RTP) setup [17] and this was the area of investigations for the
present study.
High temperature EB-PVD was discarded at this time as the time budget was to great, requiring
an extensive cool-down period spanning hours and thus only low temperature depositions were made
with EB-PVD.
Sample ID Technique Rate/Power Deposition Temp RTP-temp
ERT1 E-beam 1Å/s RT none
ERT2 E-beam 1Å/s RT 650 ,1min
ERT3 E-beam 1Å/s RT 650 ,2min
ERT4 E-beam 1Å/s RT 750 ,1min
ERT5 E-beam 1Å/s RT 750 ,2min
ERT6 E-beam 1Å/s RT 850 ,1min
ERT7 E-beam 1Å/s RT 850 ,2min
ERT8 E-beam 1Å/s RT 950 ,1min
ERT9 E-beam 1Å/s RT 950 ,2min
ERT10 E-beam 1Å/s RT 1050 ,2min
SRT1 Sputtering 50W RT none
SRT2 Sputtering 50W RT 650 ,1min
SRT3 Sputtering 50W RT 650 ,2min
SRT4 Sputtering 50W RT 750 ,1min
SRT5 Sputtering 50W RT 750 ,2min
SRT6 Sputtering 50W RT 850 ,1min
SRT7 Sputtering 50W RT 850 ,2min
SRT8 Sputtering 50W RT 950 ,1min
SRT9 Sputtering 50W RT 950 ,2min
SRT10 Sputtering 50W RT 1050 ,2min
SHT1 Sputtering 50W 600 none
SHT2 Sputtering 50W 600C 650 ,1min
SHT3 Sputtering 50W 600C 650 ,2min
SHT4 Sputtering 50W 600C 750 ,1min
SHT5 Sputtering 50W 600C 750 ,2min
SHT6 Sputtering 50W 600C 850 ,1min
SHT7 Sputtering 50W 600C 850 ,2min
SHT8 Sputtering 50W 600C 950 ,1min
SHT9 Sputtering 50W 600C 950 ,2min
SHT10 Sputtering 50W 600C 1050 ,2min
Table 4.1: Second phase experimental set-up
15
21. CHAPTER 4. EXPERIMENTAL 4.2. PHASE II - HEAT TREATMENT
4.2.1 Deposition
Electron Beam Physical Vapor Deposition
300 nm of Si was deposited using the same recipe as described in section 4.1.1, using an EvoVac
chamber from Ångstrom Engineering. The target material was highly phosphorus doped silicon and
no substrate heating was applied. Chamber pressure was 2.0 ⇥ 10 6
Torr at initiation, decreasing
to ⇡ 8.0 ⇥ 10 7
Torr during deposition. Substrate rotation was set to 7 rpm.
Sputtering
Two sets of samples were deposited, one at room temperature and one at 600 C in a Semicore
Triaxis DC/RF Magnetron Sputter using a highly phosphorus doped target. Pressure was below
2.0 ⇥ 10 6
Torr prior to argon gas introduction and the deposition pressure was 7.1 mTorr. Argon
gas flow was set to 50 SCCM. A 10 minute pre-sputtering period was included to clean the target.
4.2.2 Post deposition treatment
All samples were annealed by RTP except for one control sample. The annealing temperature were
between the 650 C to 1050 C range. Initially 1050 C was not part of the plan but was included at a
later stage as the lower temperatures did not produce desirable results. All samples were annealed
at 1 and 2 minutes at each temperature, except for the 1050 C sample which was only treated for 2
minutes. RTP was performed in nitrogen atmosphere in an AnnealSys-Micro system.
4.2.3 Characterization
Four point measurements
Initial characterization was done by four point probe measurements on all samples at three separate
points on the sample to see if the resistivity was within the range required to perform Hall e ect
measurements. A Jandel KM3-AR unit was used in high resistivity mode and auto ranging was
utilized in order to pinpoint usable current values.
X-ray di raction
All samples were characterized by X-ray di raction. A Bruker AXS D8 Discover unit was used in
✓/2✓-scan mode from 2✓ = 20 to 2✓ = 90 with increments of 0.01 at a scan rate of 0.1 seconds per
increment.
Atomic force microscopy
All samples were investigated using a Dimensions 3000 atomic force microscope (AFM) in tapping
mode.
16
23. CHAPTER 4. EXPERIMENTAL 4.3. PHASE III - SUBSTRATE PREPARATION
4.3 Phase III - Substrate preparation
As the EB-PVD did not produce desirable results in the first two phases the process was discarded
and only sputtering deposition was performed at this stage. A new pre-deposition treatment was
also included after a discussion with the supervisors where the surface topography became an area
of interest.
As the amorphous films deposited was thought to be dependent on nuclei formation and subse-
quent crystallization, it was proposed that an reactive ion etch, resulting in a topographical change
of the quartz substrate, would increase the control over the crystal growth.
As shown in table 4.2 samples were produced in pairs, both for statistical interpretation and
facilitating SIMS measurements (destructive method).
4.3.1 Pre Deposition Treatment
Three samples were etched in argon plasma by an Advanced Vacuum Vision 320 MK II reactive ion
etcher by Mikael Sjödin1
. The setup as shown in table 4.3. The resulting topography was studied us-
ing a Dimension 3000 atomic force microscope and the AFM images were produced in Gwyddion[48].
Sample 2 produced the most favorable topography; as shown in figure 4.2 the result was 1-1.5 nm
tall hillocks with a lateral width in the 20-50 nm range. Half of the samples were consequently
etched at 200 W for 5 minutes prior to deposition as shown in table 4.2, while the other half of the
samples were left untreated for reference.
Sample Power Time
ID [W] [min]
1 100 5
2 200 5
3 300 5
Table 4.3: Reactive ion etch experimental setup.
4.3.2 Deposition
As discussed in chapter 5 the room temperature sputtered sample was the only one to produce a
film resistivity low enough to yield sensible data and the high temperature sputter depositions was
therefore discarded.
Sputtering deposition power was increased to 200 W since reports by Wang et al. [17] and Jun
et al. [10] indicate that significantly higher sputtering powers in addition to keeping a substrate bias
is required to produce doped crystalline silicon. Deposition duration was decreased to 30 minutes,
aiming for a film thickness of 300 nm.
Two separate runs were initiated at room temperature and 200 C, respecively, with an initial
chamber pressure of 2.0 ⇥ 10 6
Torr. After introducing an argon flow of 50 SCCM and subsequent
plasma ignition, deposition chamber pressure was measured to be 7.0 mTorr. A pre-sputtering pe-
riod of ten minutes was used.
4.3.3 Post deposition treatment
Annealing temperatures was 1100 C but two di erent methods were used to see how di erent dura-
tion a ected the samples. RTP annealing duration was 3 minutes while furnace annealing duration
was 30 min. A AnnealSys-Micro system was used for RTP while a tube furnace was used for furnace
annealing. Both RTP and furnace annealing was performed in nitrogen-atmosphere.
4.3.4 Characterization
As available time was beginning to shrink at this point in the project only a selected number of
samples were fully characterized.
1s.b.m.sjodin@fys.uio.no
18
24. CHAPTER 4. EXPERIMENTAL 4.3. PHASE III - SUBSTRATE PREPARATION
(a) Quartz reference sample, untreated. (b) Quartz sample 1 RIE treated at 100W for 5 min
(c) Quartz sample 2 RIE treated at 200W for 5 min (d) Quartz sample 3 RIE treated at 300W for 5 min
Figure 4.1: AFM results following reactive ion etch of quartz samples
Figure 4.2: Profile of etched sample 2
Four point probe
All samples were characterized by a four point probe in the same manner as described in section
4.2.3.
19
25. CHAPTER 4. EXPERIMENTAL 4.3. PHASE III - SUBSTRATE PREPARATION
Hall E ect Measurement
It was determined that the resistivity range was within the limits of what was required for Hall
measurements and Hall measurements were performed on 9 samples as indicated in table 4.2. Hall
e ect measurements were performed using a LakeShore EM4 HGA system with a Van der Pauw
setup at room temperature using indium as contacts in the corners of the sample.
IV curve measurement were set up with start/end currents at ±10 µA and ±100 µA with cur-
rent steps at 2 µA and 20 µA depending on film resistivity.
For voltage tracking measurement the magnetic field was set to vary from -10 kG to 10 kG2
using an excitation current of 1.0 mA.
The variable field measurement was performed at a ±10 kG magnetic field. An excitation
current in the 100 µA to 1 mA range was applied, depending on the film resistivity. The resistivity
at zero field was used to calculate Hall mobility.
Atomic force microscopy
All samples were investigated using a Dimension 3000 AFM in tapping mode.
X-ray di raction
Two samples were chosen for XRD, SRT11 and SMLT7 which were low and high resistivity perform-
ers , respectively. The setup was identical to the ✓/2✓-scan mode described in section 4.2.3.
SIMS
SIMS characterization was done on all Hall e ect measured samples and performed by Alexander
Azarov 3
at MiNaLab. Both 30Si intensity and 31P concentration was measured to find phosphorus
doping concentration as well as film thickness.
2magnetic field given in gauss. 1 G corresponds to 1 ⇥ 10 4 T
3alexander.azarov@smn.uio.no
20
26. 5
R
5.1 Phase I & II
The first two phases of the project did not produce crystalline Si except for perhaps sample SRT10
(sputtered at room temperature, annealed at 1050 C for 2 min) which was the only one with a
resistivity low enough to be measured by the four point probe. Results are given in table 5.1 and
shows a high resistivity in this sample which is barely measurable with the four point probe unit
used. The sample deposited at 600 C and annealed at 1050 C did not exhibit these characteristics.
Sample Current Voltage Film Thickness Resistivity
ID [nA] [mV] [nm] [⌦ cm]
SRT10 10 90 300 1.2E+4
Table 5.1: Four point measurement results of sample SRT10
X-ray di raction corroborates the electrical results and as seen in figure 5.1 there are little or
no indication of crystal planes in the samples, except in sample SRT10 where a very slight peak is
observed close to 2✓ = 28.443 indicating Si(111)-planes [49].
Figure 5.1: X-ray di raction patterns of sample ERT1, ERT10, SRT1, SRT10, SRT3, SRT4 and SRT2.
21
27. CHAPTER 5. RESULTS 5.2. PHASE III
5.2 Phase III
5.2.1 Four Point Measurements
Phase three was a highly successful batch of samples and Si crystallized in allinvestigated samples.
As stated in section 4.3.4 initial characterization was done by four point measurements and the
results are shown in figure 5.2. The lowest resistivity was measured in samples subjected to reactive
ion etch, sputter deposition at 200 C and 30 min furnace anneal at 1100 C (SMLT7 and SMLT8).
Assuming a film thickness of 300 nm, the resistivities of these samples were, according to equation
3.1 ⇢ = 2.8⇥10 2
⌦ cm. The highest resistivity sample pair SRT15/16 had a resistivity ⇢ ⇠ 0.5 ⌦ cm.
Figure 5.2: Phase III four point measurements results at room temperature. Resistivities calculated
assuming 300 nm film thickness. The results are an average of sample pair measurements.
5.2.2 Hall E ect Measurements
Since the four point measurements showed relatively low resistivity, Hall e ect measurements was
feasible. Sample pair SMLT7/8 exhibited the lowest resistivity at ⇠ 2.8 ⇥ 10 2
⌦ cm, as well as the
highest carrier density and mobility at ⇠ 2.0⇥1019
cm 3
and ⇠ 12.0 cm2
/ Vs, respectively, as shown
in figure 5.3, 5.4 and 5.5.
Even the higher resistivity samples exhibited decent characteristics. The lowest carrier concen-
tration and mobility was found in sample SRT15 (etched and room temperature sputtered sample
with subsequent RTP treatment) with a resistivity ⇠ 0.42 ⌦ cm, a carrier density and mobility of
⇠ 4.9 ⇥ 1018
cm 3
and ⇠ 2.9 cm2
/ Vs, respectively.
22
28. CHAPTER 5. RESULTS 5.2. PHASE III
Figure 5.3: Phase III Hall e ect resistivity measurement results. The resistivity calculations used
actual thicknesses found by SIMS measurements.
Figure 5.4: Phase III Hall e ect carrier density measurement results.
23
29. CHAPTER 5. RESULTS 5.2. PHASE III
Figure 5.5: Phase III Hall e ect mobility measurement results.
5.2.3 Secondary Ion Mass Spectrometry
To determine the actual thickness and phosphorous concentration of the samples, SIMS was used.
The results are shown in figure 5.6 and 5.7 and show a similar phosphorus concentration in all
samples. Film thicknesses varies from 260 - 280 nm in the samples sputtered at 200 C and 280 -
300 nm in the samples sputtered at room temperature.
In figure 5.8 phosphorus concentration in sample SMLT7 is plotted against depth showing a
similar phosphorus concentration throughout the film. Film thickness can be derived from this.
24
30. CHAPTER 5. RESULTS 5.2. PHASE III
Figure 5.6: Results from thickness measurements by SIMS characterization on Hall measured sam-
ples.
Figure 5.7: Results of SIMS characterization on Hall e ect measured samples. Phosphorous con-
centration given is an average of the measured concentrations throughout the film.
25
31. CHAPTER 5. RESULTS 5.2. PHASE III
Figure 5.8: Phosphorus concentration vs depth in sample SMLT7. The first five points left out
because of inaccuracy of SIMS measurements near the surface.
26
32. CHAPTER 5. RESULTS 5.2. PHASE III
5.2.4 Atomic force microscopy
All samples were investigated with AFM to compare the pre-deposition treated samples with the
untreated ones, both in surface height root mean square (RMS) and topography. As figure 5.9 shows,
the etched and unetched di ers significantly; the untreated sample with the lowest RMS have an
RMS of almost 1.5 times that of the highest among the treated samples.
AFM images substantiate this as figure 5.10 shows. Figure 5.10e and 5.10f are untreated samples
having a visibly higher roughness than the treated samples shown in figure 5.10a to 5.10d.
Figure 5.9: Root Mean Square statistical measurements of the surface height of phase III samples
by AFM characterization.
27
33. CHAPTER 5. RESULTS 5.2. PHASE III
(a) SMLT8 - RIE (b) SRT18 - RIE
(c) SMLT6 - RIE
(d) SRT16 - RIE
(e) SMLT4 - no RIE (f) SRT11 - no RIE
Figure 5.10: Atomic force microscope images of phase III samples.
28
34. CHAPTER 5. RESULTS 5.2. PHASE III
5.2.5 X-ray di raction
Only two samples were measured by XRD at this phase, as described in section 4.3.4. In figure 5.11
and 5.12 reflection peaks are observed close to 2✓ = 28.443 and 2✓ = 47.303 indicating the presence
of Si (111) and (220) planes, respectively[49].
In sample SMLT7, a peak is observed close to 2✓ = 32.965 indicating In (101) plane [49]. This
is due to the indium contacts used in Hall e ect measurements of this sample. No such peak is
observed in figure 5.12 as no Hall e ect measurements were made on sample SRT11.
In both XRD patterns there are clear peaks close to 2✓ = 44.74 , 2✓ = 65.135 and 2✓ = 78.229 ,
indicating Al (200) (220) (311) planes [49], respectively, and these originate from the aluminum
sample holder.
Comparing the two samples shows higher intensities and more defined peaks at both the Si
(111) reflection and the Si (220) reflection in sample SMLT7, an indication of a higher degree of
crystallinity in this sample.
Figure 5.11: X-ray di raction pattern of sample SMLT7. This sample was measured by Hall e ect
measurements where indium contacts were used.
Figure 5.12: X-ray di raction pattern of sample SRT11.
29
35. 6
D
When looking at why the first two phases did not yield any crystalline silicon, a couple of parameters
stands out; in particular deposition technique as well as the lack of post deposition treatment.
As shown in the results section none of the samples deposited by electron beam physical vapor
deposition showed any signs of crystallinity, indicating an amorphous film even after post deposition
annealing. The reasons for this is unknown; other groups such as Jamil et al. [50] have succeeded in
depositing polycrystalline silicon, but further investigation of this was discarded as sputtering was
chosen as the favored method.
Sputtered samples investigated from phase I and II were almost exclusively showing signs of
amorphous films, except for one sample, sputtered at room temperature and RTP treated at 1050 C
for 2 minutes. This sample did show slight signs of crystallinity as well as a resistivity within the
measurable range by four point measurement. This sample (referred to as SRT10 in text) indicated
that high sputtering temperatures was a potential unfavorable deposition condition and this laid
the foundation for further investigations.
From literature it was found that nuclei formation plays a role in post deposition crystallization
[14] and a pre deposition reactive ion etch was therefore included in the experimental setup to try
and manipulate the formation of nuclei. The etch was designed to change the topography to match
typical crystal grain sizes of about 50 nm. As seen in figure 4.2 this was achieved and by studying
the resulting topography, such as comparing figure 4.1c and 5.10a, a similarity in topography is
observed, indicating a certain control of crystal growth, although the sample in 5.10a seem to have
a slightly rougher surface with broader bumps.
The RIE does not seem to enhance the electrical characteristics of the film. As can be seen in
figure 5.3 it seems like the un-etched samples performs better in the room temperature sputtered
ones; in the 200 C sputtered ones it is opposite as the RIE samples perform slightly better, hence
the RIE process does not seem to enhance electrical properties.
On the other hand there is clear indications that electrical properties largely depend on sputter-
ing settings, temperature and power, and annealing duration as figures 5.3, 5.4 and 5.5 clearly shows.
These figures show that furnace annealing produces higher quality films than the RTP treatment
does, indicating that the increase in duration from 3 to 30 minutes at 1100 C makes a big di erence;
possibly both in crystallizing the a-Si as well as activating the phosphorus dopants present in the
deposited films.
The increase in power from phase I and II to phase III changes the results radically and it seems
that 200 W sputtering power is far better suited for post deposition solid phase crystallization than
sputter deposition at 50 W, possibly due to the densification of the a-Si film [51]. Comparing the
results in figure 5.3 (phase III) with the results in table 5.1 (phase II) the di erence becomes obvious:
the highest resistivity measured in phase III samples (SRT15): ⇢ ⇠ 0.5 ⌦cm
vs. resistivity measured in phase II sample (SRT10): ⇢ ⇠ 1.2 ⇥ 104
⌦cm
As this indicates, the poor performers in phase III performed relatively well, exhibiting decent
electrical properties and even though the furnace annealing resulted in the best films, the rapid
thermal processing does produce satisfactory films.
30
36. 7
C
Depositing a highly doped silicon thin film with desirable electrical properties was achieved by sput-
tering a highly doped silicon target, both at room temperatures and 200 C, either untreated or re-
active ion etched, with subsequent annealing at 1100 C for 3 and 30 minutes.
It is found that a relatively high sputtering power is needed to deposit films suitable for sub-
sequent solid phase crystallization. Longer annealing duration seems to yield a higher degree of
crystallinity and an increase in the number of activated dopants.
It is also shown that crystallization of silicon in this experimental setup requires relatively high
annealing temperatures (> 1000 C) to both crystallize and activate dopants.
31
37. B
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