The document summarizes the bus architecture and control signals of the Intel 8086/8088 microprocessors. It describes the 20-line address bus and 16-bit or 8-bit data bus depending on the specific chip. It also outlines the control signals for memory access and other functions. Maximum and minimum modes are discussed which change the control structure and allow compatibility with 8-bit peripherals. The 8288 clock generator chip is mentioned as providing the necessary control signals when the 8086 is in maximum mode with an external coprocessor.
3. 8086/8088 Busses
• Address Bus
– 20 address lines so a 220
byte address space.
– Pins A0-A19 provide the address
– For 8086, A0-A15 are multiplexed with D0-D15 to form AD0-AD15
– For 8088, A0-A7 are multiplexed with D0-D7 to form AD0-AD7
• Data Bus
– For 8086, 16 bit data bus D0-D15 (multiplexed as AD0-AD15)
– For 8088, 8 bit data bus D0-D7 (multiplexed as AD0-AD7)
• Control Bus
– For memory access, the following pins are used:
RD’, WR’, M/IO’, DT/R’, DEN’, ALE, BHE’
– Other input signals to control 8086 performance:
clk ,reset , ready , hold , test’, intr , nmi ,mn’/mx
- The intr and hold are acknowledged through intra and holda
respectively.
13. 8086/8088 Detailed Memory Interface
8086/8
Control
Multiplexed
Addr/Data
Latches
Buffers
Demultiplexing
Control
Address
Data
Address
Decoding
Unique
per device
M
E
M
O
R
Y
Partial
Address
CS’,WE’,OE’
16. 8086 maximum & minimum modes
• The mode is controlled by MN/MX.
• Maximum mode is obtained by connecting MN/MX to high and minimum mode
is by connecting it to high.
• Having two different modes (minimum and maximum) is used only 8088/8086.
• Each mode enables a different control structure.
• Minimum mode operation and control signals are very similar to those of 8085.
• So 8085 8-bit peripherals can be used with 8086 without special considerations.
• Easy and least expensive way to build single processor systems
18. Maximum mode
• Maximum mode is designed to be used with a coprocessor exists in
the system.
• All the control signals (except RD ) are not generated by the
microprocessor.
• But we still need those control signals.
• Solution:
• 8288.
21. QS1 QS0
0 0 No instruction taken from queue.
0 1 First byte of current instruction taken from queue.
1 0 Queue flushed.
1 1 Byte other than first byte taken from queue.