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Ino 1 gbps link design
1.
2. Objective
To demonstrate a point to point 1Gbps
communication link over virtex 5 ml507.
To demonstrate a single node to multiple node
communication link of same speed.
To design a multiple point to single point
communication link.
Performance analysis of the link by eye diagram
analysis.
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3. Xilinx virtex 5 ml507
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SFP module
FPGA
4. Xilinx Virtex 5 ml507
ML507 is an FXT platform that supports RocketIO
GTX transceivers (up to 3.125 Gbps).
Assume 4.5 Mbps from each RPC
(1x16) x (1x32) x 4.5 Gbps = 2.3 Gbps
We will need 10 servers for each half module
Clocking-
Programmable system clock generator chip
External clocking via SMAs (two differential pairs)
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5. Experimental Setup
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Tx and Rx through SMA ports on the Virtex boards
6. Challenges
Pre-emphasis of the transmitter to desired level.
Design the equalization block of the receiver
according to the communication link.
Transmitter and receiver clock synchronization and
frame detection.
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8. Receiver Equalization
There are two types of equalization techniques that
can be implemented in the block.
Continuous Time Linear Equalization and Decision
Feedback Equalization
Decision Feedback Equalization has been used.
DFE automatically adapts to time-varying properties
of the communication channel.
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12. Performance Analysis of
Communication Link
Performance analysis of the communication link is
done by calculating Q- factor and estimating BER
from Q-factor.
BER= (½)erfc(Q/ 1.414)
Configuration:
1. Point to Point Link.
2. Single Transmitter and Multiple Receiver.
3. Multiple Transmitter and Single Receiver.
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13. Point to Point Communication
Link at Different Data rate
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16. Estimation of BER from Q-
Factor
Data Rate Q Value BER Estimation
500 Mbps 6.73 8.5 E -10
750 Mbps 6.53 3.8 E -10
1 Gbps 6.41 7.5 E -09
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17. Multiple Tx to Single Rx
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18. Single Tx to Multiple Rx
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19. Estimation of BER from Q-
Factor
Network
Configuration
Q Value Estimation of BER
Single Transmitter
multiple Receiver 5.4 3.44 E-06
Multiple
Transmitter single
Receiver
6.1 1.2 E -09
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Tx through SMA, T-splitter, Rx also on SMA
20. Future Work
Timing synchronization
Optical Rx (Tx is working)
Live demonstration with (1x16) x (1x32) splitters
RPC DAQ v3 board design
SFP instead of Wiznet+RJ45
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21. Physical layer design
Aggregate data from two rows of 16 RPCs each
Can support up to 4.5 Mbps of data from each RPC