Exceptions and Interrupts on Cortex-M

CS/ECE 5780/6780
Embedded Systems Design

Lecture 7, part 2: Exceptions and
Interrupts

Thomas Schmid
thomas.schmid@utah.edu
February 5, 2013
Tuesday, February 5, 13

Announcements
• Are we using C, or ARM or Thumb?
• What’s the difference between ARM & Thumb?
– ARM (assembly): always 32-bit
– Thumb (assembly): always 16-bit
– Thumb-2 (assembly): Mixed 16 and 32-bit
• Who clears interrupt, software or hardware? How to find
out?
– Read the datasheet.

2

System Timer Register Map
System Timer Register Map
The System Timer base address resides at 0x40005000 and extends to address 0x40005FFF in the
Cortex-M3 memory map.

Table 17-1 • System Timer Register Map
Reset
Register Name Address R/W Value Description
TIM1_VAL (TIMx_VAL) 0x40005000 R 0x0 Current value of Timer 1
TIM1_LOADVAL (TIMx_LOADVAL) 0x40005004 R/W 0x0 Load value for Timer 1
TIM1_BGLOADVAL (TIMx_BGLOADVAL) 0x40005008 R/W 0x0 Background load value for Timer 1
TIM1_CTRL (TIMx_CTRL) 0x4000500C R/W 0x0 Timer 1 Control register
TIM1_RIS (TIMx_RIS) 0x40005010 R/W 0x0 Timer 1 raw interrupt status
TIM1_MIS (TIMx_MIS) 0x40005014 R 0x0 Timer 1 masked interrupt status
TIM2_VAL (TIMx_VAL) 0x40005018 R 0x0 Current value of Timer 2
TIM2_LOADVAL (TIMx_LOADVAL) 0x4000501C R/W 0x0 Load value for Timer 2
TIM2_BGLOADVAL (TIMx_BGLOADVAL) 0x40005020 R/W 0x0 Background load value for Timer 2
TIM2_CTRL (TIMx_CTRL) 0x40005024 R/W 0x0 Timer 2 Control register
TIM2_RIS (TIMx_RIS) 0x40005028 R/W 0x0 Timer 2 raw interrupt status
TIM2_MIS (TIMx_MIS) 0x4000502C R 0x0 Timer 2 masked interrupt status
TIM64_VAL_U 0x40005030 R 0x0 Upper 32-bit word in 64-bit mode
TIM64_VAL_L 0x40005034 R 0x0 Lower 32-bit word in 64-bit mode
TIM64_LOADVAL_U 0x40005038 R/W 0x0 Upper 32-bit load value word in 64-bit
mode
TITM64_LOADVAL_L 0x4000503C R/W 0x0 Lower 32-bit load value word in 64-bit
mode
TIM64_BGLOADVAL_U 0x40005040 R/W 0x0 Upper 32-bit background load value in 64-
bit mode
TIM64_BGLOADVAL_L 0x40005044 R/W 0x0 Lower 32-bit background load value in 64-
bit mode
TIM64_CTRL 0x40005048 R/W 0x0 Control register in 64-bit mode
TIM64_RIS 0x4000504C R/W 0x0 Raw interrupt status in 64-bit mode
TIM64_MIS 0x40005050 R 0x0 Masked interrupt status in 64-bit mode
TIM64_MODE 0x40005054 R/W 0x0 System Timer dual 32-bit or 64-bit mode
3

SmartFusion Microcontroller Subsystem User’s Guide

Timer x Control Register
Table 17-5 • TIMx_CTRL
Bit Reset
Number Name R/W Value Description
31:3 Reserved R/W 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 TIMxINTEN R/W 0x0 Timer x Interrupt Enable. When the counter reaches zero, an interrupt is
signaled to the Cortex-M3 Nested Vectored Interrupt Controller; IRQ20
for Timer x, IRQ21 for Timer 2.
0 = Timer x interrupt disabled
1 = Timer x interrupt enabled
Writing this register while the System Timer is set to 64-bit mode has no
effect. Reading this register while the System Timer is set to 64-bit mode
returns the reset value.
1 TIMxMODE R/W 0x0 Timer x Mode.
0 = Timer x in Periodic Mode. If TIMxENABLE = 1 when the counter
reaches zero the counter is reloaded from the value in the
TIMxLOADVAL register and begins counting down immediately.
1 = Timer x in One-Shot mode. If TIMxENABLE = 1 when the counter
reaches zero the counter stops counting. To start the counter again, the
user must load TIMxLOADVAL with a non-zero value or set the Timer to
Periodic mode by clearing TIMxMODE to 0.
0 TIMxENABLE R/W 0x0 Timer x Enable
0 = Timer x disabled
1 = Timer x enabled
Setting to 1 enables the timer and starts it counting from the current
value in TIMx_VAL unless TIMx_VAL is 0, in which case TIMx_VAL is
loaded from TIMx_LOADVAL.
4

System Timer

Timer x Raw Interrupt Status Register
Table 17-6 • TIMx_RIS
Bit Reset
31:1 Reserved R/W 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 TIMx_RIS R/W 0x0 Timer x Raw Interrupt Status
0 = Timer x has not reached zero
1 = Timer x has reached zero at least once since this bit was last cleared
(by a reset or by writing 1 to this bit).
Writing a 1 to this bit clears the bit and the interrupt, writing a zero has no
effect.

Timer x Masked Interrupt Status Register
Table 17-7 • TIMx_MIS
Bit Reset

5 31:1 Reserved R 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should

Minute Quiz

6

Minute Quiz

What is the first interrupt that fires
on a Cortex-M3?

7

Exercise: How many preemption priorities and subpriority levels
do we get on the Smart Fusion if we set Priority Group to 5?

-3 Reset Preempt levels Subpriority levels
-2 NMI with priority
-1 Hard Fault group set to 5
0x00 Programmable 0x00 0x00
0x08 Exceptions 0x08
0x10 0x10
0x18 0x18
0x20 0x20
0x28 0x40 0x28
0x30 0x30
0x38 0x38
0x40
0x48
0x80

0xc0 0xc0
0xc8
0xe0
0xd0
0xe8
0xd8
0xf0
0xe0
0xf8
0xe8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0xf0
0xf8
8 Preempt Sub

PRIMASK, FAULTMASK, and BASEPRI

• What if we quickly want to disable all interrupts?

• Write 1 into PRIMASK to disable all interrupt except NMI
– MOV R0, #1
– MSR PRIMASK, R0
• Write 0 into PRIMASK to enable all interrupts
• FAULTMASK is the same as PRIMASK, but also blocks
hard fault (priority -1)

• What if we want to disable all interrupts below a certain
priority?
• Write priority into BASEPRI
– MOV R0, #0x60
9 – MSR BASEPRI, R0

Question
Assume BASE_PRIO_REG is set to the
programmable interrupt priority register,
and the following code runs:
movw r0, #:lower16:INT_PRIO_REG
movt r0, #:upper16:INT_PRIO_REG
mov r1, #61
strb r, [r0, #31]
MOV R0, #0x60
MSR BASEPRI, R0

Will interrupt 31 still interrupt your
10
code?

Outline
• Minute quiz
• Finish up interrupts
• Graduate student presentations
• Final projects

11

What exactly is an interrupt handler?

12

Vector Tables
Vector Table
When an exception takes place and is being handled by the Cortex-M3, the processor will
eed to•locate the starting address of the Cortex-M3 needs to know thein
Upon an interrupt, the exception handler. This information is stored
e vector table. By default, the vector table starts at address zero, and the vector address is
address of the interrupt handler (function pointer)
ranged according to the exception number times 4 (see Table 7.6).
• After powerup, vector table is located at Up
Table 7.6 Exception Vector Table After Power
0x00000000
Address Exception Number Value (Word Size)
0x00000000 – MSP initial value
0x00000004 1 Reset vector (program counter initial value)
0x00000008 2 NMI handler starting address
0x0000000C 3 Hard fault handler starting address
… … Other handler starting address

ince the address 0x0 should be boot code, usually it will either be Flash memory or ROM
evices, •and the value cannot be changed at runinterrupt handlers at runtime
Can be relocated to change time. However, the vector table can be
located (vector tablelocations in the Code or RAM region where the RAM is so that w
to other memory offset register)
an change the handlers during run time. This is done by setting a register in the NVIC called
e vector table offset register (address 0xE000ED08). The address offset should be aligned
the vector table size, extended to the power of 2. For example, if there are 32 IRQ inputs,
13
eTuesday, February 5, 13 of exceptions will be 32 ϩ 16 (system exceptions) ϭ 48. Extending it to the
total number

Vector Table in SoftConsole
• Located in startup_a2fxxxm3.s

• Put at 0x00000000 in linker script

14

Interrupt Handlers

15

Interrupt Handler in GNU C

• We can overwrite the predefined interrupt handlers

__attribute__((__interrupt__)) void Timer1_IRQHandler()
{
MSS_TIM1_disable_irq();
MSS_TIM1_clear_irq();
…
NVIC_ClearPendingIRQ( Timer1_IRQn );
}

int main()
{
…
MSS_TIM1_enable_irq();
NVIC_EnableIRQ( Timer1_IRQn );
…
while(1){}
}

16

Interrupt Service Routines

1. Automatic saving of registers upon exception
• PC, PSR, R0-R3, R12, LR pushed on the stack
2. While bus busy, fetch exception vector
3. Update SP to new location
4. Update IPSR (low part of PSR) with new exception
number
5. Set PC to vector handler
6. Update LR to special value EXC_RETURN

• Several other NVIC registers get updated
• Latency: as short as 12 cycles
17

9
Interrupt Stacking
Address
N-8 N-4 N-32 N-28 N-24 N-20 N-16 N-12
(HADDR)

Data
PC PSR R0 R1 R2 R3 R12 LR
(HWDATA)
Chapter 3
Time
31 30 29 28 27 Figure 9.1 23:20 19:16 Sequence
26:25 24 Stacking 15:10 9 8 7 6 5 4:0

APSR N Z C V Q

ues of PC and PSR are stacked ﬁrst so that instruction fetch can be started early (w
IPSR Exception Number

modiﬁcation of PC) and the IPSR can be updated early. After stacking, SP will b
EPSR ICI/IT T ICI/IT
to N-32 (0 ϫ 20), and the stacked data arrangement in the stack memory will loo
le 9.1. Figure 3.3 Program Status Registers (PSRs) in the Cortex-M3

31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8 7 6 5 4:0
Table 9.1 Stack Memory Content After Stacking and Stacking Order
xPSR N Z C V Q ICI/IT T ICI/IT Exception Number
Address Data Push Order
Figure 3.4 Combined Program Status Registers (xPSR) in–the Cortex-M3
Old SP (N) -Ͼ (Previously pushed data)
18 From: The Definitive Guide to the ARM Cortex-M3
(N-4) February 5,read the program status registers using the MRS instruction. You can also change the
You can 13
Tuesday, PSR 2

processors) is required to restore the system status so that the interrupted program can resume
Return from ISR
normal execution. There are three ways to trigger the interrupt return sequence; all of them use
the special value stored in the LR in the beginning of the handler (see Table 9.2).

• 3 ways to return from an ISR
Table 9.2 Instructions that Can be Used for Triggering Exception Return
Return Instruction Description
BX ϽregϾ If the EXC_RETURN value is still in LR, we can use the BX LR instruction to
perform the interrupt return.
POP {PC}, or Very often the value of LR is pushed to the stack after entering the exception
POP {...., PC} handler. We can use the POP instruction, either a single POP or multiple POPs, to
put the EXC_RETURN value to the program counter. This will cause the processor
to perform the interrupt return.
LDR, or LDM It is possible to produce an interrupt return using the LDR instruction with PC as
the destination register.

1 • Unstack and reset SP
EXC_RETURN has values with bit[31:4] and are all 1 (i.e., 0xFFFFFFFX); the last 4 bits deﬁne the return
information. More information on the EXC_RETURN value is covered later in this chapter.
• Update NVIC registers
151

19
.indd 151

Nested Interrupts

• Built into the Cortex-M3 (not every MCU has this)
• Make sure main stack is large enough!

• Three methods:
– Tail Chaining
– Late Arrival
– Preemption

20

Interrupt Behavio
Tail Chaining
Interrupt #1

Interrupt #2
Interrupt Interrupt exits Interrupt exits
Event #1
Interrupt Service Interrupt Service
Routine #1 Routine #2
Main Program Main Program
Stacking Unstacking
Processor
State
Thread Mode Handler Mode Handler Mode Thread Mode

Figure 9.2 Tail Chaining of Exceptions

• If first interrupt has same or higher priority
Arrivals
• Skip stacking/unstacking for efficiency
er feature that improves interrupt performance is late arrival exception handling. When
eption takes place and the processor has started the stacking process, and if during this
a new exception arrives with higher preemption priority, the late arrival exception will
cessed ﬁrst.

uted as soon as the stacking completes.
Late Arrival
Interrupt #1
(Low Priority)

Interrupt #2
(High Priority)

Processor
State Thread Exception Sequence Handler #2

Data Bus Stacking

Instruction
Bus Thread Handler Instruction Fetch

Vector Fetch

Figure 9.3 Late Arrival Exception Behavior

re on the Exception Return Value
• Main stack must be able to hold maximum
n entering annumberhandler, the LR is updated to a special value called EXC_RETURN
exception of preemptions!
the upper 28 bits all set to 1. This value, when loaded into the PC at the end of the
153

FIGURE 9.4 Instruction Thread Handler instruction fetch
bus
EXC_RETURN
Late Arrival Exception Behavior.
Vector fetch

FIGURE 9.4
Table 9.2 Description of Bit
Late Arrival Exception Behavior. Fields in EXC_RETURN Value

Bits 31:4 3 2 1 0

Descriptions 0xFFFFFFF Return mode Return stack Reserved; Process state
Table 9.2 Description of Bit Fields in EXC_RETURN Value
(thread/handler) must be 0 (Thumb/ARM)
Bits 31:4 3 2 1 0

Descriptions 0xFFFFFFF Return mode Return stack Reserved; Process state
(thread/handler) must be 0 (Thumb/ARM)
Table 9.3 Allowed EXC_RETURN Values on Cortex-M3
Value Condition
Allowed values on the ARM Cortex-M3 modeCortex-M3
Table 9.3 Allowed EXC_RETURN Values onReturn to handler
0xFFFFFFF1
0xFFFFFFF9 Return to thread mode and on return use the main stack
Value
0xFFFFFFFD Condition
Return to thread mode and on return use the process stack
0xFFFFFFF1 Return to handler mode
0xFFFFFFF9 Return to thread mode and on return use the main stack
0xFFFFFFFD
Bit 0 indicates the process state being used after to thread mode return. Since the Cortex-M3 supports
Return the exception and on return use the process stack
only the Thumb® state, bit 0 must be 1. The valid values (for the Cortex-M3) are shown in Table 9.3.
If the thread is using the MSP (main stack), the value of LR will be set to 0xFFFFFFF9 when it
enters anindicates theand 0xFFFFFFF1 when aafter the exception is entered, as the Cortex-M3 supports
Bit 0 exception, process state being used nested exception return. Since shown in Figure 9.5. If
only the Thumb® state, (process stack), the value of LR would be Cortex-M3) are shown in Table 9.3.
the thread is using PSP bit 0 must be 1. The valid values (for the 0xFFFFFFFD when entering the ﬁrst
exceptionthread is using the for entering astack), the value ofas shown in Figure 0xFFFFFFF9 when it
If the and 0xFFFFFFF1 MSP (main nested exception, LR will be set to 9.6.
enters an exception, EXC_RETURN number format, you cannot perform interrupt returnsFigure 9.5. If
As a result of the and 0xFFFFFFF1 when a nested exception is entered, as shown in to an address
23
thethe 0xFFFFFFF0–0xFFFFFFFF memory range. LR would since this The Definitive in entering theCortex-M3
From: address is Guide to the ARM
in thread is using PSP (process stack), the value of However, be 0xFFFFFFFD when a nonexecutable ﬁrst

9.6 More on the Exception Return Value 1
Preemption (Thread with Main Stack)
Interrupt #1
(Low priority)

Interrupt #2
(High priority)

Interrupt exit
Stacking
Interrupt service Interrupt
routine #2 exit
Execution Interrupt
status event #1
Interrupt service
routine #1 Unstacking
Main program

Main stack Main stack Main stack

Handler Handler Handler
Thread mode Thread mode
mode mode mode

LR 5 0xFFFFFFF9 LR 5 0xFFFFFFF1

RE 9.5
24

Different Concepts of Interrupt Sharing
Universal Asynchronous Receiver/Transmitter (UART) Peripherals

• Number of potential interrupts usually larger than interrupt
Interrupt Identification Register (IIR)
lines availability on Core
Table 15-8 • IIR

• One peripheral often only has one interrupt
Bit
Number Name R/W Reset Value Description
7:6 Mode R 0b11 Always 0b11. Enables FIFO mode.
• Different types of 5:4
events are stored in a statusnot rely on the value of a reserved bit. To
Reserved R 0 Software should register
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.

• Example, UART 3:0 Interrupt
identification
bits
R 0b0001 0b0110 = Highest priority. Receiver line status interrupt due
to overrun error, parity error, framing error or break
interrupt. Reading the Line Status Register resets this
– IIR, 0x40000008 interrupt.
0b0100 = Second priority. Receive data available interrupt
modem status interrupt. Reading the Receiver Buffer
Register (RBR) or the FIFO drops below the trigger level
resets this interrupt.
0b1100 = Second priority. Character timeout indication
interrupt occurs when no characters have been read from the
RX FIFO during the last four character times and there was at
least one character in it during this time. Reading the Receive
Buffer Register (RBR) resets this interrupt.
0b0010 = Third priority. Transmit Holding Register Empty
interrupt. Reading the IIR or writing to the Transmit Holding
Register (THR) resets the interrupt.
0b0000 = Fourth priority. Modem status interrupt due to
Clear to Send, Data Set Ready, Ring Indicator, or Data Carrier
Detect being asserted. Reading the Modem Status Register
resets this interrupt.
This register is read only; writing has no effect. Also see
Table 15-9.
25
Table 15-9 • Interrupt Identification Bit Values

ISR Sharing, i.e., Callbacks in C
• There is only one interrupt handler
• Functions have to “subscribe” for events
• Callbacks
– Driver provides function to register a function pointer
– Driver stores function pointers in list
– Upon interrupt, each registered function gets called
typedef void (*radioalarm_handler_t)(void);
radioalarm_handler_t radio_alarm_fired;

void RadioAlarm_init(radioalarm_handler_t handler)
{
radio_alarm_fired = handler;
}

__attribute__((__interrupt__)) void Timer1_IRQHandler()
{
alarm_state = FREE;
MSS_TIM1_disable_irq();
MSS_TIM1_clear_irq();
NVIC_ClearPendingIRQ( Timer1_IRQn );
(*(radio_alarm_fired))(); // call the callback function
26 }

Common Problems and Pit-Falls

• Too many interrupts
– Your core can’t keep up with handling interrupts
• Concurrency issues
– One interrupt handler modifies global variables
– Can be avoided using atomic sections protected through
PRIMASK
• Lost interrupts
– It can happen that an interrupt doesn’t get treated by the
Core
– State machine and peripheral has to be aware of this
possibility
– Danger for deadlocks
27

Summary
• Overwrite default Interrupt Handler

• Initialization
– Enable interrupt in NVIC
– Enable interrupt in Peripheral

• Upon Interrupt
– Clear interrupt in Peripheral
– Clear pending bit in NVIC
– Potentially disable interrupts temporarily

28

Graduate Student Presentations

29

Graduate Student Presentations
• Graduate students will present one embedded system
– Processor and system architecture
– Tools and software for programming, hackability
– Platforms
– Why does this system exist
– Demo it

• 19 graduate students
• 5 Lectures between Spring Break & Open House
• 4 students per lecture (~15 min)
• You can pick your platform

• Sign up: http://goo.gl/HUAXN
30

You propose a platform!

Selection due by Feb 21st

Talk to me about the platform you want to choose
(Office Hours or by appointment)

31

Projects

32

Start Thinking about Projects!
Picking a Project Idea: Think BIG to
Picking
a
Project
Idea:
Think
BIG
to
Start
Start
Thinking Big: Segway Example Simplified 373 Project

Problems Solution
•Scale: To Big…Accommodates adults! •Scale: Scale Down 1’ High
•Power: Large Power Source and Actuators •Power: Low Power, Hobby Servo Actuators
•Complex Control
Complex •Simple Control
•Gyro Stabilized •“Tail” controls variable resistor
•High Center of Gravity •Low Center of Gravity
33 Slides from Matt Smith

Types Of Projects: Music
Air Guitar

Touch key matrix to
emulate fret board
of guitar. Fabricate
with PC board.

Guitar Pick air
Music created by
action is modeled
sending MIDI codes
with 3 axis
to MIDI synthesizer.
accelerometer.

Types Of Projects: Concept
Auto Balancing Teeter Totter
l

Angle position
controlled by
propeller speed

Angle is maintained
Infrared distance
with feedback
sensor to measure
control.
height
Construction by Knex


Types Of Projects: Robotic
Knight Ryder
h d
• Featured gyros and accelerometers
for inertial guidance (really).
• Spoiler was added to maintain
traction and stability at high speeds!
(probably cosmetic).

Graphics
display
indicating
heading
and
position

Types Of Projects: Gaming
Space Invaders
Intense gaming
I t i
Classic game
in the 373 lab!
controllers: N64
and N8

Graphics
display
indicating
the
termination
t i ti Slides from Matt
37 of Earth! Smith

Types Of Projects: Measurement
Radar
d
IR and Ultrasonic
Sensor for Ranging

Servo provided angular
sweep.
p

Advertisement
Reflections plotted as function of
angle and distance

Types Of Projects: Research
Wireless Power Monitoring

Objectives Processor (LPC1114)
• Contained in 1 cubic inch PCB Design! AC thru plug
• Wireless transmitting info to
central monitor and control
• Low power
• Low cost (in quantity)
Radio
(CC2520)

Interconnect Points Fold
Power Monitor Circuit
to Connect Cube Sides
(ADE7753)
39

3D PCB and Conductive Ink

40

Quadcopter

41

Idea, Starting Points
• Review
Last
Year
ECE/CS
5780/6780
Projects
• h6p://wiesel.ece.utah.edu/redmine/projects/ece5780-‐s12-‐groups
• Review
Past
UM
373
Projects
• h6p://www.eecs.umich.edu/courses/eecs373/Labs/Web/projects.html

• Search
YouTube
373
projects

• Provides
Sense
of
Scale

• Review
Cornel
Projects
Web
Site
• h6p://instruct1.cit.cornell.edu/courses/ee476/FinalProjects/

• Feedback
control
oriented,
but
lots
of
applicaQons

• More
devices
to
consider

• Research
Oriented
Projects
• Prof
Schmid
will
provide
a
list
soon
• YOU!
• Have
a
big
cup
of
coﬀee
and
dream

• Pick
something
you
want
to
do!!

• Think
about
all
the
embedded
applicaQons
around
you

• Consider
variants

• Consider
improvements

• Research
the
applicaQon
(know
something
about
it!)

• Discuss
your
ideas
with
potenQal
partners
and
friends

42 • Discuss
your
ideas
with
staﬀ


Forming Groups
• Group sizes: 2 – 4
p
• Larger Groups
– Advantages: Do more complex projects
– Disadvantages: Challenging group management,
unknown relationships
• Smaller Groups
– Advantages: Group dynamic is simpler, task
management, known relationship, etc
– Di d t
Disadvantages: Possibly li it project complexity
P ibl limits j t l it
• Start with existing Lab Partner or form new
43
groups

Proposal
• Due: 3/5, Tuesday in Lecture
• Contents
– List of group members
– Goal Statement: In general terms describe your project
– Functional Specification
List and describe high level functions
high level functional diagram
– Preliminary Component List
• Proposal Reviews
– March 6th (Wednesday) & 7th (Thursday)

44

Proposal Example
Goal Statement
For our project we intend to build a sound level
meter. Sound level meters are used in applications ranging
from environmental noise management to balancing sound
systems in concert halls.
Our meter will approximate the Extech Model
407764.
407764 We will attempt emulate some the meter s basic
meter’s
functionality, but with out the same precision or reference
accuracy.

The meter will h
h ll have the f ll
h following b
basic f
functions:
1. Sound level measurement with A and C frequency
weighting
2. Time weighting from 1 – 100 seconds
g g
3. Linear and logarithmic display of sounds level
4. Manual (4 ranges) and auto ranging
5. Data logging for 1 hour
6.
6 PC interface t h
i t f to hyper t
terminal f ASCII fil ti
i l for file time series fil
i file
storage of data log.
45

Functional Description
• Sound Measurement
– Microphone: Commercial sound meters use expensive microphones. We
will use a simple audio mic that will not have the same sensitivity, but can
be frequency compensated.
– Signal Conditioning: An audio amplifier will have to be provided to provide
gain to the ADC.
– Signal Conditioning: An anti aliasing filter will have to be provided to for
audio frequencies. We will use an active filter.
• Data Acquision
– The ACE will be setup to acquire data with 10 bit resolution and sample
frequency of 40khz.
• Frequency Measurement
– An FFT over the audio range will be performed using SmartFusion FFT
core.
• Display
p y
– Display sound level digitally, simply analog meter graphic, measurement
modes, etc.
• Key Pad
– U input: measurement modes, display options, etc
User i t t d di l ti t
46

Functional Diagram

Audio
Serial Interface
Microphone,
to Computer
Amplifier,
Anti alias Filter SmartFusion Kit
User I t f
U Interface
ADC
FFT
Log Memory
Keypad
d Display

47

Questions?

Comments?

Discussion?

Write on a paper:

- One point that really sticks out about this lecture
- One point that was unclear about this lecture
48

Exceptions and Interrupts on Cortex-M

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