1. ARM architecture
The ARM architecture describes a family of RISC-based computer processors designed
and licensed by British company ARM Holdings. It was first developed in the 1980s.
ARM Holdings itself does not manufacture its own electronic chips, but licenses its
designs to other semiconductor manufacturers. Using a RISC based approach to
computer design, ARM processors require significantly fewer transistors than
processors that would typically be found in a traditional computer. The benefits of this
approach are lower costs, less heat, and less power usage, traits that are desirable for
use in light, portable, battery-powered devices such as smart phones and tablet
computers. The reduced complexity and simpler design allows companies to build a
low-energy system on a chip for an embedded system incorporating memory,
interfaces, radios, etc.
In the C programming language, the loop is:
while (i != j) {
if (i > j)
i -= j;
else
j -= i;
}
In ARM assembly, the loop is:
loop: CMP Ri, Rj ; set condition "NE" if (i != j),
; "GT" if (i > j),
; or "LT" if (i < j)
SUBGT Ri, Ri, Rj ; if "GT" (greater than), i = i-j;
SUBLT Rj, Rj, Ri ; if "LT" (less than), j = j-i;
BNE loop

2. FEATURES
• 32-bit ARM7TDMI-S microcontroller.
• 32 kB of on-chip static RAM and 512 kB of on-chip Flash program memory. 128 bit
wide interface/accelerator enables high speed 60 MHz operation.
• Single Flash sector or full chip erase in 400ms and programming of 256 bytes in 1 ms.
• One (LPC2131/2132) or two (LPC2138) 8 channel 10-bit A/D converters provide a
total of up to 16 analog inputs, with conversion times as low as 2.44 s per channel.
• Single 10-bit D/A converter provides variable analog output.
• Two 32-bit timers/counters (with four capture and four compare channels each), PWM
unit (six outputs) and watchdog.
• Real-time clock equipped with independent power and clock supply permitting
extremely low power consumption in powersave modes.
• Multiple serial interfaces including two UARTs (16C550), two Fast I2C (400 kbit/s),
SPI™ and SSP with buffering and variable data length capabilities.
• Vectored interrupt controller with configurable priorities and vector addresses.
• Up to 47 of 5 V tolerant general purpose I/O pins.
• Up to nine edge or level sensitive external interrupt pins available.
• 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked
Loop (PLL) with settling time of 100microseconds.
• On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
• Power saving modes include Idle and Power-down.
• Individual enable/disable of peripheral functions as well as peripheral clock scaling
down for additional power optimization.
• Processor wake-up from Power-down mode via external interrupt.
• Single power supply chip with Power-On Reset (POR) and Brown-Out Detection
(BOD) circuits:
- CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.

3. Device No. of Pins On-Chip On-chip No. of 10- No. of 10-
RAM FLASH bit AD bit DA
Channels Channels
LPC2138 64 32K 512K 2x8 1
ARM7TDMI-S PROCESSOR
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory
systems can operate continuously. Typically, while one instruction is being executed, its
successor is being decoded, and a third instruction is being fetched from memory. The
ARM7TDMI-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue. The key idea behind
THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S
processor has two instruction sets:
• The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because THUMB
code operates on the same 32-bit register set as ARM code.

4. THUMB
To improve compiled code-density, processors since the ARM7TDMI (released in 1994)
have featured Thumb instruction set, which have their own state. (The "T" in "TDMI"
indicates the Thumb feature.) When in this state, the processor executes the Thumb
instruction set, a compact 16-bit encoding for a subset of the ARM instruction set. Most
of the Thumb instructions are directly mapped to normal ARM instructions. The space-
saving comes from making some of the instruction operands implicit and limiting the
number of possibilities compared to the ARM instructions executed in the ARM
instruction set state.
In Thumb, the 16-bit opcodes have less functionality. For example, only branches can
be conditional, and many opcodes are restricted to accessing only half of all of the
CPU's general purpose registers. The shorter opcodes give improved code density
overall, even though some operations require extra instructions. In situations where the
memory port or bus width is constrained to less than 32 bits, the shorter Thumb
opcodes allow increased performance compared with 32-bit ARM code, as less
program code may need to be loaded into the processor over the constrained memory
bandwidth.
Duty cycle
A duty cycle is the percent of time that an entity spends in an active state as a fraction of the total time
under consideration. The term is often used pertaining to electrical devices, e.g., switching power
supplies. It is also sometimes used pertaining to living systems such as the firing of action
potentials by neurons. In an electrical device, a 60% duty cycle means the power is on 60% of the time
and off 40% of the time. The "on time" for a 60% duty cycle could be a fraction of a second – or for say,
irrigation pumps, days – depending on how long the device's period is. Here one period is the length of
time it takes for the device to go through a complete on/off cycle.