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Ben van der Zon BlueBird Back-end electonics assembly and packaging Acive Positionning “ Less is Better”
Background High Density Integration of semiconductor systems ambient intelligence Autonomous smart systems: more functionality per mm cube Improved performance More than Moore: Beyond a few atomic diameters ? more functionality per mm square More Moore:
Background High Density Integration of semiconductor systems ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Background High Density Integration of semiconductor systems Source: University of California
Market drivers for 3D stacking of IC’s. ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Background High Density Integration of semiconductor elements: 3D-TSV TSV creation Carrier bonding Placing Collective bonding Molding Singulation Cleaning Wafer thinning Dicing Picking Inspection TSV filling
General trends related to packaging and assembly ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Cost of ownership 0,00 10,00 20,00 30,00 40,00 50,00 60,00 70,00 80,00 B1 Carrier wafer bonding B2 Thinning B3.1 Application resist B3.2 Patterning B3.3 Development B3.4 DRIE etching B4 TSV filling B5 UBM & bumping B6 Waferprobing B7 Dicing B8 Pick, carrier de-bonding B9 Inspection B10 Place B11 Die bonding B12 Dicing B13 Flip chip or die bonding B14 Encapsulation B15 Singulation B16 End inspection & test B17 Marking B18 Packing Cost of Ownership [$/wafer] Cost of Ownership = 300 $ Cost of Ownership = 150 $
Technologies required  (post front-end) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Low cost ,[object Object],[object Object],[object Object]
Pick & Place state-of-the-Art
Typical P&P clycle ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],1 2 3 4 5 6 7 8
Accurate and fast Pick & Place Go ==> Look ==> Find ==> Place ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Alignment for assembly ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Alignment concept less is better Simultaneous measurement Of die and substrate ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Further developments ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
P&P topologies
Fluid selfassembly Tolley et al

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09.50 dhr van der zon

  • 1. Ben van der Zon BlueBird Back-end electonics assembly and packaging Acive Positionning “ Less is Better”
  • 2. Background High Density Integration of semiconductor systems ambient intelligence Autonomous smart systems: more functionality per mm cube Improved performance More than Moore: Beyond a few atomic diameters ? more functionality per mm square More Moore:
  • 3.
  • 4. Background High Density Integration of semiconductor systems Source: University of California
  • 5.
  • 6. Background High Density Integration of semiconductor elements: 3D-TSV TSV creation Carrier bonding Placing Collective bonding Molding Singulation Cleaning Wafer thinning Dicing Picking Inspection TSV filling
  • 7.
  • 8. Cost of ownership 0,00 10,00 20,00 30,00 40,00 50,00 60,00 70,00 80,00 B1 Carrier wafer bonding B2 Thinning B3.1 Application resist B3.2 Patterning B3.3 Development B3.4 DRIE etching B4 TSV filling B5 UBM & bumping B6 Waferprobing B7 Dicing B8 Pick, carrier de-bonding B9 Inspection B10 Place B11 Die bonding B12 Dicing B13 Flip chip or die bonding B14 Encapsulation B15 Singulation B16 End inspection & test B17 Marking B18 Packing Cost of Ownership [$/wafer] Cost of Ownership = 300 $ Cost of Ownership = 150 $
  • 9.
  • 10. Pick & Place state-of-the-Art
  • 11.
  • 12.
  • 13.
  • 14.
  • 15.