Device Modeling of Delay using PSpice

1. IC Modeling
Device Modeling of
Delay
Using PSpice
15OCT2014
Bee Technologies Inc
Tsuyoshi Horigome

2. Equivalent Circuit
R1
100MEG
R2
100MEG
Delay _IN
Delay_OSC
0 0
1
if (V(Delay _IN)>3 & V(Delay_OSC)>3,1m,0)
GVALUE
G1
IN-OUT+
OUT-IN+
GVALUE
if (V(Delay _IN)<1 & V(Delay_OSC)>3,1m,0)
IN-OUT+
OUT-IN+
G2
C1
1n
IC = 0
G3
IN-OUT+
OUT-IN+
if (V(CAL_01)<0.01,1m,0)
GVALUE
if (V(CAL_01)>3.5,1m,0)
GVALUE
IN-OUT+
OUT-IN+
G4
R3
100MEG
0 0
0
0
0
CAL_01 IN_Delay _P
if (V(IN_Delay _P,IN_Delay_M)>0.01,5,0)
OUT-E1
IN+
IN-OUT+
EVALUE
OUT-E2
IN+
IN-OUT+
EVALUE
if (V(Delay_OUT)>4,{LV},{HV})
R4
10
C2
10p
IC = 0
1
R5
100MEG
0
0
0
0
RL
100MEG
0
Delay_OUT
V
V
V
IN_Delay_M
PARAMETERS:
HV = 2.5
LV = 1.25
V1
5Vdc
V2
0
V1 = 0
V2 = 5
TD = 0
TR = 1n
TF = 1n
PW = 1u
PER = 10u
0
Delay

3. Simulation
Input
Output
OSC
Node of CAL_01
Delay Time