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Device Modeling of UVLO using PSpice
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Tsuyoshi Horigome
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Device Modeling of UVLO using PSpice
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Device Modeling of UVLO using PSpice
1.
IC Modeling Device
Modeling of UVLO Using PSpice UVLO(Under Voltage Lock Out) 低電圧ロックアウト。DC-DCコンバーターで、入力電圧が一定以下 の場合、内部回路をスタンバイ状態にして誤動作を防止する機能 13OCT2014 Bee Technologies Inc Tsuyoshi Horigome
2.
V1 V1 =
0 V2 = 18 TD = 0 TR = 100u TF = 100u PW = 10n PER = 200.01u R1 10 OUT-E1 EVALUE OUT-E2 R2 100MEG R3 100MEG IN+ IN-OUT+ if (V(UVLO_IN_P)>(V(UVLO_IN_M)+0.01),{VREF},0) IN+ IN-OUT+ EVALUE if (V(UVLO_OUT)>4,{LV},{HV}) UVLO_IN_P 0 0 0 0 C1 1p IC = 0 UVLO_OUT UVLO_IN_M PARAMETERS: VREF = 5 HV = 12 LV = 8 V V UVLO Equivalent Circuit
3.
Simulation Input Output
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