How to Effectively Monitor SD-WAN and SASE Environments with ThousandEyes
Synchronous Buck Converter using LTspice
1. Synchronous-Buck Converter Circuit
• Synchronous-Buck Converter Circuit
• Test Setup
• Test Circuit
• Synchronous-Buck Controller
• MOSFET: TPC8014
• Inductor L1: Würth Elektronik Inductor
• Capacitor C9: 820uF (25V)
• Switching Waveform
• High Side MOSFET(QH): VGS, VDS, ID
• Low Side MOSFET(QL): VGS, VDS, ID
• Gate Drive Signal
• VIN-VOUT
• VOUT,RIPPLE
• Output Inductor Voltage and Current
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2. Synchronous-Buck Converter Circuit
Duty Cycle (D)
≈ Vin/Vout,
D = 0.368
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3. Test Setup
Power Supply:
Measurement Waveform VCC 12V
VIN 5V
Test Circuit
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4. Test Circuit Schematic
Synchronous-Buck Converter using TPS5618 controller from Texas Instruments
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5. Test Circuit (Breadboard)
Q1
Q2
Controller
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6. Test Circuit (Top View)
L1
C9
C10
Controller
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7. Synchronous-Buck Controller (1/2)
Synchronous-Buck Controller Circuit with IC Synchronous-Buck Controller Block Model
TPS5618 from Texas Instruments (Open Loop Setting)
HIDR
High side gate driver
Low side gate driver
LODR
• The Syn-Buck_Ctrl is a block model that generates gate drive pulse signal to control MOSFET
switches of the Synchronous-Buck Converter. The duty cycle, switching frequency, and the
switching dead-time are input into the model to match the real circuit.
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8. Synchronous-Buck Controller (2/2)
Parameters
• FREQ = Switching frequency, set to match
the measurement switching frequency.
PARAMETERS: • D = Duty Cycle, calculated by D≈VOUT/VIN
•
FREQ = 152kHz
D = 0.36
DHDR1 RHDR1 tdly = HDR and LDR dead-time, the tdly is
U1 Dclmp 0.01
tdly = 80n AND2_ABM N7 set to match the measurement dead time
Rdly 1
N4
N5 N6
HDR value.
Dclmp RHDR2 CHDR Dead-time, the time
1k
Cdly 1 VOH = 12 DHDR2 0.01 1n when QH and QL
Pulse {tdly /1k} VOL = 0
0 are both off
Control 0
Signal 1/frequency
U5 U2
INV_ABM AND2_ABM
N1 N2
Rdly 2
N3 LDR
VOH = 1.709
VOL = 0
1k
V1 Cdly 2 VOH = 8
{tdly /1k} VOL = 0
TD = {1/FREQ}
TR = 1n 0
TF = 1n Dead-time
0 V1 = 0
V2 = 1.709 generator
PW = {D/FREQ}
PER = {1/FREQ}
The Syn-Buck_Ctrl Equivalent Circuit
Gate drive signal (measurement)
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14. High Side MOSFET(QH): VGS, VDS, ID
Measurement Simulation
VGS(Q1) VGS(Q1)
VDS(Q1)
VDS(Q1)
ID(Q1) ID(Q1)
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15. Low Side MOSFET(QL): VGS, VDS, ID
Measurement Simulation
VGS(Q2) VGS(Q2)
VDS(Q2)
VDS(Q2)
ID(Q2) ID(Q2)
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16. Gate Drive Signal
Measurement Simulation
VGS(Q1) VGS(Q1)
VGS(Q2) VGS(Q2)
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17. VIN – VOUT
Measurement Simulation
VIN VIN
VOUT VOUT
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18. VOUT,RIPPLE
Measurement Simulation
VOUT,RIPPLE VOUT,RIPPLE
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19. Output Inductor Voltage and Current
Measurement Simulation
V(L)
V(L)
I(L)
I(L)
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