SlideShare a Scribd company logo
1 of 42
Download to read offline
KL 2164
DIGITAL ELECTRONICS
Multi Level Gate Circuit
              Pn. Wan Nurdiana Wan Ibrahim
                    nurdiana@eng.ukm.my
Multi-Level Gate Circuits
Terminology:
1. AND-OR circuit means a two-level circuit composed of a
   level of AND gates followed by an OR gate at the output.
2. OR-AND circuit means a two-level circuit composed of a
   level of OR gates followed by an AND gate at the output.
3. OR-AND-OR circuit means a three-level circuit composed of
   a level of OR gates followed by a level of AND gates
   followed by an OR gate at the output.
4. Circuit of AND and OR gates implies no particular ordering
   of the gates; the output gate may be either AND or OR.

                               2
Four-Level Realization of Z


Each node on a tree
diagram represents a
gate, and the number
of gate inputs is
written beside each
node.




                       3
4
Z = (AB + C) (D+ E + FG) + H

Number of level?
Number of gate?
Number of gate input?



Change to three levels by partially multiplying it
out :
Z = (AB + C) (D+ E + FG) + H




                                               5
Three -Level Realization of Z




              6
Example
Find a circuit of AND and OR gates to realize
f (a, b, c, d) = Ʃ m(1, 5, 6, 10, 13, 14)

 Consider solutions with two levels of gates and three levels
  of gates.
 Try to minimize the number of gates and the total number of
  gate inputs.
 Assume that all variables and their complements are
  available as inputs.

First, simplify f by using a Karnaugh map.

                                 7
8
This leads
directly to a
two-level
AND-OR gate
circuit.




                9
Factoring yields
     f=?




           10
Both of these solutions have an OR gate at the output. A
solution with an AND gate at the output might have fewer
gates or gate inputs.
A two-level OR-AND circuit corresponds to a product-of-sums
expression for the function. This can be obtained from the 0′s
on the Karnaugh map as follows:

f ′ = c′d + ab′c′ + cd + a′b′c


leads directly to a two-level OR-AND circuit.



                               11
12
To get a three-level circuit with an AND gate output, we
partially multiply out using (X + Y)(X + Z) = X + Y Z:




It would require four levels of gates to realize;
 however, if we multiply out d′(a + b) and d(a′ + b), we get


which leads directly to a three-level AND-OR-AND circuit.



                                 13
14
For this particular example,
the best two-level solution had an AND gate at the output
the best three-level solution had an OR gate at the output.
In general, to be sure of obtaining a minimum solution, must find both the
circuit with the AND-gate output and the one with the OR-gate output.




                                        15
NAND gates
The small circle (or “bubble”) at the gate output indicates
inversion
 the NAND gate = AND gate followed by an inverter.

The gate output is
                        F = (ABC)′ = A′ + B′ + C′




                                   16
NOR gates
Shows a three-input NOR gate.
NOR gate = OR gate followed by an inverter.
The gate output is
                    F = (A + B + C)′ = A′B′C′




                                17
Functionally Complete Set of Gates
AND and NOT are a functionally complete set
of gates because OR can also be realized
using AND and NOT:




                      18
NAND Gates
Similarly, any function can be realized using only
NAND gates:




                             19
Design of Two-Level NAND-Gate Circuits

A two-level circuit composed of AND and OR gates is easily
converted to a circuit composed of NAND gates or NOR gates

Step 1: using F = (F′)′
Step 2 : applying DeMorgan′s laws:


             (X1 + X2 + … + Xn)′ = X1′ X2′…Xn′


             (X1 X2…Xn)′ = X1′ + X2′ + … + Xn′


                                20
Design of Two-Level NAND-Gate Circuits –cont.

Example illustrates conversion of a minimum sum-of-products form
to several other two-level forms:


  F = A + BC′ + B′CD = [(A + BC′ + B′CD)′ ]′          AND-OR
    = [A′ • (BC′)′ • (B′CD)′]′                    NAND-NAND
    = [A′ • (B′ + C) • (B + C′ + D′)]′               OR-NAND
    = A + (B′ + C)′ + (B + C′ + D′)′                  NOR-OR



                                  21
Design of Two-Level NOR-Gate Circuits

Want a two-level circuit containing only NOR gates;
 start with the minimum product-of-sums form for F.
F can be written in the following two-level forms:


   F = (A + B + C)(A + B′ + C′)(A + C′ + D)                 OR-AND
     = {[(A + B + C)(A + B′ + C′)(A + C′ + D)]′ }′
     = [(A + B + C)′ + (A + B′ + C′)′ + (A + C′ + D)′]′    NOR-NOR
     = (A′B′C′ + A′BC + A′CD′)′                           AND-NOR
     = (A′B′C′)′ • (A′BC)′ • (A′CD′)′                     NAND-AND


                                     22
Eight Basic Forms for Two-Level Circuits




                    23
The other eight possible two-level forms:
(AND-AND,OR-OR,OR-NOR,AND-NAND,NAND-NOR,NOR-NAND
etc ) degenerate ;cannot realize all switching functions.
Consider, for example, the following NAND-NOR circuit:




From this example, it is clear that the NAND-NOR form can realize
only a product of literals and not a sum of products.


                                24
Design of Minimum Two-Level NAND-NAND
Circuits



Procedure for designing a minimum two-level NAND-NAND circuit:

1. Find a minimum sum-of-products expression for F.
2. Draw the corresponding two-level AND-OR circuit.
3. Replace all gates with NAND gates leaving the gate
interconnection unchanged. If the output gate has any single literals
as inputs, complement these literals.



                                  25
F = l1 + l2 + • • • + P1 + P2 + • • •




     F = (l1′l2′ • • • P1′P2′ • • •)′




26
Design of Multi-Level NAND- and NOR-Gate
                     Circuits

 The following procedure may be used to design multi-level NAND-gate
 circuits:

1. Simplify the switching function to be realized.
2. Design a multi-level circuit of AND and OR gates. The output
   gate must be OR. AND gate outputs cannot be used as AND-
   gate inputs; OR-gate outputs cannot be used as OR-gate
   inputs.
3. Number the levels starting with the output gate as level 1.
   Replace all gates with NAND gates, leaving all interconnections
   between gates unchanged, leave the inputs to levels 2,4,6,…
   unchanged. Invert any literals which appear as inputs to levels
   1,3,5,…
                                   27
28
Alternative Gate Symbols



Logic designers who design complex digital systems often find it
convenient to use more than one representation for a given type of
gate. For example, an inverter can be represented by




                                 29
Alternative Gate Symbols



Equivalent gate
symbols based on
DeMorgan′s Laws




                       30
NAND Gate Circuit Conversion




                         31
Conversion to NOR Gates




           32
Conversion of AND-OR Circuit to NAND Gates




                   33
Design of Two-Level, Multiple-Output
                     Circuits

Solution of digital design problems often requires the realization
of several functions of the same variables. Although each
function could be realized separately, the use of some gates in
common between two or more functions sometimes leads to a
more economical realization.
Example:
Design a circuit with four inputs and three outputs which realizes
the functions




                                 34
35
Draw the Circuit Realization




                       36
Multiple-Output Realization of
          Equations




                    Realization of functions with
                    shared gates (lower overall cost)
                    (7 Gates)




              37
Another example of sharing gates among multiple outputs to
   reduce cost.

f1 = Ʃ m(2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
f2 = Ʃ m(2, 3, 5, 6, 7, 10, 11, 14, 15)
f3 = Ʃ m(6, 7, 8, 9, 13, 14, 15)


Draw the Karnaugh Map:




                                          38
Minimal Solution




     39
In this example, the
best solution is
obtained by not
combining the circled 1
with adjacent 1’s.




                          40
The solution with the
maximum number of
common terms is not
necessarily the best
solution, as illustrated
by this example.




                           41
Multi-Level Circuit Conversion to NOR Gates




                                   The procedure for
                                   design of single-
                                   output, multi-level
                                   NAND- and NOR-
                                   gate circuits also
                                   applies to multiple-
                                   output circuits




                    42

More Related Content

What's hot

Nand logic gate electronics plc microcontroller series
Nand logic gate electronics plc microcontroller seriesNand logic gate electronics plc microcontroller series
Nand logic gate electronics plc microcontroller seriesHumayun Rashed
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Satya P. Joshi
 
basic logic gates
 basic logic gates basic logic gates
basic logic gatesvishal gupta
 
Nand and nor as a universal gates
Nand and nor as a universal gatesNand and nor as a universal gates
Nand and nor as a universal gatesKaushal Shah
 
Digital Logic Gates and RAID Explained v1.3
Digital Logic Gates and RAID Explained v1.3Digital Logic Gates and RAID Explained v1.3
Digital Logic Gates and RAID Explained v1.3Howard Wong
 
The logic gate circuit
The logic gate circuitThe logic gate circuit
The logic gate circuitroni Febriandi
 
Logic gate class 12
Logic gate class 12Logic gate class 12
Logic gate class 12Nipun Shah
 
Digital logic gate and its application
Digital logic gate and its applicationDigital logic gate and its application
Digital logic gate and its applicationAbdullah Al Masud
 
CSEC Physics Review - Introduction To Logic Gates
CSEC Physics Review - Introduction To Logic GatesCSEC Physics Review - Introduction To Logic Gates
CSEC Physics Review - Introduction To Logic GatesKevin Small
 
Basic Gates in Digital Logic
Basic Gates in Digital LogicBasic Gates in Digital Logic
Basic Gates in Digital LogicISMT College
 

What's hot (20)

Nand gate
Nand gateNand gate
Nand gate
 
Nand logic gate electronics plc microcontroller series
Nand logic gate electronics plc microcontroller seriesNand logic gate electronics plc microcontroller series
Nand logic gate electronics plc microcontroller series
 
Logic gates
Logic gatesLogic gates
Logic gates
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
 
Logic gates (1)
Logic gates (1)Logic gates (1)
Logic gates (1)
 
basic logic gates
 basic logic gates basic logic gates
basic logic gates
 
Nand and nor as a universal gates
Nand and nor as a universal gatesNand and nor as a universal gates
Nand and nor as a universal gates
 
Logic Gates
Logic GatesLogic Gates
Logic Gates
 
Logic Gates
Logic GatesLogic Gates
Logic Gates
 
Logical Gates
Logical GatesLogical Gates
Logical Gates
 
Digital Logic Gates and RAID Explained v1.3
Digital Logic Gates and RAID Explained v1.3Digital Logic Gates and RAID Explained v1.3
Digital Logic Gates and RAID Explained v1.3
 
Logic not gate tutorial with logic gate truth table
Logic not gate tutorial with logic gate truth tableLogic not gate tutorial with logic gate truth table
Logic not gate tutorial with logic gate truth table
 
The logic gate circuit
The logic gate circuitThe logic gate circuit
The logic gate circuit
 
Logic gate class 12
Logic gate class 12Logic gate class 12
Logic gate class 12
 
Logic gates
Logic gatesLogic gates
Logic gates
 
LOGIC GATES
LOGIC GATESLOGIC GATES
LOGIC GATES
 
Digital logic gate and its application
Digital logic gate and its applicationDigital logic gate and its application
Digital logic gate and its application
 
Logic gate
Logic gateLogic gate
Logic gate
 
CSEC Physics Review - Introduction To Logic Gates
CSEC Physics Review - Introduction To Logic GatesCSEC Physics Review - Introduction To Logic Gates
CSEC Physics Review - Introduction To Logic Gates
 
Basic Gates in Digital Logic
Basic Gates in Digital LogicBasic Gates in Digital Logic
Basic Gates in Digital Logic
 

Similar to Nand or gates ver_student

Lec9 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Com...
Lec9 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Com...Lec9 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Com...
Lec9 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Com...Hsien-Hsin Sean Lee, Ph.D.
 
Chapter 4 combinational circuit
Chapter 4 combinational circuit Chapter 4 combinational circuit
Chapter 4 combinational circuit GulAhmad16
 
Find all hazards in this circuit. Redesign the circuit as a three-le.pdf
Find all hazards in this circuit.  Redesign the circuit as a three-le.pdfFind all hazards in this circuit.  Redesign the circuit as a three-le.pdf
Find all hazards in this circuit. Redesign the circuit as a three-le.pdfArrowdeepak
 
CMOS Topic 6 -_designing_combinational_logic_circuits
CMOS Topic 6 -_designing_combinational_logic_circuitsCMOS Topic 6 -_designing_combinational_logic_circuits
CMOS Topic 6 -_designing_combinational_logic_circuitsIkhwan_Fakrudin
 
Combinational logic circuits design and implementation
Combinational logic circuits design and implementationCombinational logic circuits design and implementation
Combinational logic circuits design and implementationssuserca5764
 
universal_gates nannnnnnanannananananad.ppt
universal_gates nannnnnnanannananananad.pptuniversal_gates nannnnnnanannananananad.ppt
universal_gates nannnnnnanannananananad.pptTobyTheMasterBuilder
 
DLD BOOLEAN EXPRESSIONS
DLD BOOLEAN EXPRESSIONSDLD BOOLEAN EXPRESSIONS
DLD BOOLEAN EXPRESSIONSnaresh414857
 
Online quesion deldunit-1-to_unit-4
Online quesion deldunit-1-to_unit-4Online quesion deldunit-1-to_unit-4
Online quesion deldunit-1-to_unit-4shivnarayan34
 
CMOS Combinational_Logic_Circuits.pdf
CMOS Combinational_Logic_Circuits.pdfCMOS Combinational_Logic_Circuits.pdf
CMOS Combinational_Logic_Circuits.pdfSouravRoyElectronics
 

Similar to Nand or gates ver_student (20)

12.Digital Logic.pdf
12.Digital Logic.pdf12.Digital Logic.pdf
12.Digital Logic.pdf
 
VLSI & E-CAD Lab Manual
VLSI & E-CAD Lab ManualVLSI & E-CAD Lab Manual
VLSI & E-CAD Lab Manual
 
ECAD lab manual
ECAD lab manualECAD lab manual
ECAD lab manual
 
e CAD lab manual
e CAD lab manuale CAD lab manual
e CAD lab manual
 
Lec9 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Com...
Lec9 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Com...Lec9 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Com...
Lec9 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Com...
 
Deld lab manual
Deld lab manualDeld lab manual
Deld lab manual
 
Chapter 4 combinational circuit
Chapter 4 combinational circuit Chapter 4 combinational circuit
Chapter 4 combinational circuit
 
11.ppt
11.ppt11.ppt
11.ppt
 
Find all hazards in this circuit. Redesign the circuit as a three-le.pdf
Find all hazards in this circuit.  Redesign the circuit as a three-le.pdfFind all hazards in this circuit.  Redesign the circuit as a three-le.pdf
Find all hazards in this circuit. Redesign the circuit as a three-le.pdf
 
CMOS Topic 6 -_designing_combinational_logic_circuits
CMOS Topic 6 -_designing_combinational_logic_circuitsCMOS Topic 6 -_designing_combinational_logic_circuits
CMOS Topic 6 -_designing_combinational_logic_circuits
 
Combinational logic circuits design and implementation
Combinational logic circuits design and implementationCombinational logic circuits design and implementation
Combinational logic circuits design and implementation
 
universal_gates nannnnnnanannananananad.ppt
universal_gates nannnnnnanannananananad.pptuniversal_gates nannnnnnanannananananad.ppt
universal_gates nannnnnnanannananananad.ppt
 
9525.ppt
9525.ppt9525.ppt
9525.ppt
 
Lecture 5
Lecture 5Lecture 5
Lecture 5
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
 
DLD BOOLEAN EXPRESSIONS
DLD BOOLEAN EXPRESSIONSDLD BOOLEAN EXPRESSIONS
DLD BOOLEAN EXPRESSIONS
 
Online quesion deldunit-1-to_unit-4
Online quesion deldunit-1-to_unit-4Online quesion deldunit-1-to_unit-4
Online quesion deldunit-1-to_unit-4
 
CMOS Combinational_Logic_Circuits.pdf
CMOS Combinational_Logic_Circuits.pdfCMOS Combinational_Logic_Circuits.pdf
CMOS Combinational_Logic_Circuits.pdf
 
C046051216
C046051216C046051216
C046051216
 
design pro.pptx
design pro.pptxdesign pro.pptx
design pro.pptx
 

Recently uploaded

Philosophy of Education and Educational Philosophy
Philosophy of Education  and Educational PhilosophyPhilosophy of Education  and Educational Philosophy
Philosophy of Education and Educational PhilosophyShuvankar Madhu
 
DUST OF SNOW_BY ROBERT FROST_EDITED BY_ TANMOY MISHRA
DUST OF SNOW_BY ROBERT FROST_EDITED BY_ TANMOY MISHRADUST OF SNOW_BY ROBERT FROST_EDITED BY_ TANMOY MISHRA
DUST OF SNOW_BY ROBERT FROST_EDITED BY_ TANMOY MISHRATanmoy Mishra
 
CHUYÊN ĐỀ DẠY THÊM TIẾNG ANH LỚP 11 - GLOBAL SUCCESS - NĂM HỌC 2023-2024 - HK...
CHUYÊN ĐỀ DẠY THÊM TIẾNG ANH LỚP 11 - GLOBAL SUCCESS - NĂM HỌC 2023-2024 - HK...CHUYÊN ĐỀ DẠY THÊM TIẾNG ANH LỚP 11 - GLOBAL SUCCESS - NĂM HỌC 2023-2024 - HK...
CHUYÊN ĐỀ DẠY THÊM TIẾNG ANH LỚP 11 - GLOBAL SUCCESS - NĂM HỌC 2023-2024 - HK...Nguyen Thanh Tu Collection
 
How to Manage Cross-Selling in Odoo 17 Sales
How to Manage Cross-Selling in Odoo 17 SalesHow to Manage Cross-Selling in Odoo 17 Sales
How to Manage Cross-Selling in Odoo 17 SalesCeline George
 
How to Solve Singleton Error in the Odoo 17
How to Solve Singleton Error in the  Odoo 17How to Solve Singleton Error in the  Odoo 17
How to Solve Singleton Error in the Odoo 17Celine George
 
UKCGE Parental Leave Discussion March 2024
UKCGE Parental Leave Discussion March 2024UKCGE Parental Leave Discussion March 2024
UKCGE Parental Leave Discussion March 2024UKCGE
 
In - Vivo and In - Vitro Correlation.pptx
In - Vivo and In - Vitro Correlation.pptxIn - Vivo and In - Vitro Correlation.pptx
In - Vivo and In - Vitro Correlation.pptxAditiChauhan701637
 
CapTechU Doctoral Presentation -March 2024 slides.pptx
CapTechU Doctoral Presentation -March 2024 slides.pptxCapTechU Doctoral Presentation -March 2024 slides.pptx
CapTechU Doctoral Presentation -March 2024 slides.pptxCapitolTechU
 
Diploma in Nursing Admission Test Question Solution 2023.pdf
Diploma in Nursing Admission Test Question Solution 2023.pdfDiploma in Nursing Admission Test Question Solution 2023.pdf
Diploma in Nursing Admission Test Question Solution 2023.pdfMohonDas
 
Maximizing Impact_ Nonprofit Website Planning, Budgeting, and Design.pdf
Maximizing Impact_ Nonprofit Website Planning, Budgeting, and Design.pdfMaximizing Impact_ Nonprofit Website Planning, Budgeting, and Design.pdf
Maximizing Impact_ Nonprofit Website Planning, Budgeting, and Design.pdfTechSoup
 
How to Add Existing Field in One2Many Tree View in Odoo 17
How to Add Existing Field in One2Many Tree View in Odoo 17How to Add Existing Field in One2Many Tree View in Odoo 17
How to Add Existing Field in One2Many Tree View in Odoo 17Celine George
 
Ultra structure and life cycle of Plasmodium.pptx
Ultra structure and life cycle of Plasmodium.pptxUltra structure and life cycle of Plasmodium.pptx
Ultra structure and life cycle of Plasmodium.pptxDr. Asif Anas
 
2024.03.23 What do successful readers do - Sandy Millin for PARK.pptx
2024.03.23 What do successful readers do - Sandy Millin for PARK.pptx2024.03.23 What do successful readers do - Sandy Millin for PARK.pptx
2024.03.23 What do successful readers do - Sandy Millin for PARK.pptxSandy Millin
 
What is the Future of QuickBooks DeskTop?
What is the Future of QuickBooks DeskTop?What is the Future of QuickBooks DeskTop?
What is the Future of QuickBooks DeskTop?TechSoup
 
Patient Counselling. Definition of patient counseling; steps involved in pati...
Patient Counselling. Definition of patient counseling; steps involved in pati...Patient Counselling. Definition of patient counseling; steps involved in pati...
Patient Counselling. Definition of patient counseling; steps involved in pati...raviapr7
 
Drug Information Services- DIC and Sources.
Drug Information Services- DIC and Sources.Drug Information Services- DIC and Sources.
Drug Information Services- DIC and Sources.raviapr7
 
The basics of sentences session 10pptx.pptx
The basics of sentences session 10pptx.pptxThe basics of sentences session 10pptx.pptx
The basics of sentences session 10pptx.pptxheathfieldcps1
 
General views of Histopathology and step
General views of Histopathology and stepGeneral views of Histopathology and step
General views of Histopathology and stepobaje godwin sunday
 
5 charts on South Africa as a source country for international student recrui...
5 charts on South Africa as a source country for international student recrui...5 charts on South Africa as a source country for international student recrui...
5 charts on South Africa as a source country for international student recrui...CaraSkikne1
 

Recently uploaded (20)

Philosophy of Education and Educational Philosophy
Philosophy of Education  and Educational PhilosophyPhilosophy of Education  and Educational Philosophy
Philosophy of Education and Educational Philosophy
 
DUST OF SNOW_BY ROBERT FROST_EDITED BY_ TANMOY MISHRA
DUST OF SNOW_BY ROBERT FROST_EDITED BY_ TANMOY MISHRADUST OF SNOW_BY ROBERT FROST_EDITED BY_ TANMOY MISHRA
DUST OF SNOW_BY ROBERT FROST_EDITED BY_ TANMOY MISHRA
 
CHUYÊN ĐỀ DẠY THÊM TIẾNG ANH LỚP 11 - GLOBAL SUCCESS - NĂM HỌC 2023-2024 - HK...
CHUYÊN ĐỀ DẠY THÊM TIẾNG ANH LỚP 11 - GLOBAL SUCCESS - NĂM HỌC 2023-2024 - HK...CHUYÊN ĐỀ DẠY THÊM TIẾNG ANH LỚP 11 - GLOBAL SUCCESS - NĂM HỌC 2023-2024 - HK...
CHUYÊN ĐỀ DẠY THÊM TIẾNG ANH LỚP 11 - GLOBAL SUCCESS - NĂM HỌC 2023-2024 - HK...
 
How to Manage Cross-Selling in Odoo 17 Sales
How to Manage Cross-Selling in Odoo 17 SalesHow to Manage Cross-Selling in Odoo 17 Sales
How to Manage Cross-Selling in Odoo 17 Sales
 
How to Solve Singleton Error in the Odoo 17
How to Solve Singleton Error in the  Odoo 17How to Solve Singleton Error in the  Odoo 17
How to Solve Singleton Error in the Odoo 17
 
UKCGE Parental Leave Discussion March 2024
UKCGE Parental Leave Discussion March 2024UKCGE Parental Leave Discussion March 2024
UKCGE Parental Leave Discussion March 2024
 
In - Vivo and In - Vitro Correlation.pptx
In - Vivo and In - Vitro Correlation.pptxIn - Vivo and In - Vitro Correlation.pptx
In - Vivo and In - Vitro Correlation.pptx
 
CapTechU Doctoral Presentation -March 2024 slides.pptx
CapTechU Doctoral Presentation -March 2024 slides.pptxCapTechU Doctoral Presentation -March 2024 slides.pptx
CapTechU Doctoral Presentation -March 2024 slides.pptx
 
Diploma in Nursing Admission Test Question Solution 2023.pdf
Diploma in Nursing Admission Test Question Solution 2023.pdfDiploma in Nursing Admission Test Question Solution 2023.pdf
Diploma in Nursing Admission Test Question Solution 2023.pdf
 
Maximizing Impact_ Nonprofit Website Planning, Budgeting, and Design.pdf
Maximizing Impact_ Nonprofit Website Planning, Budgeting, and Design.pdfMaximizing Impact_ Nonprofit Website Planning, Budgeting, and Design.pdf
Maximizing Impact_ Nonprofit Website Planning, Budgeting, and Design.pdf
 
Prelims of Kant get Marx 2.0: a general politics quiz
Prelims of Kant get Marx 2.0: a general politics quizPrelims of Kant get Marx 2.0: a general politics quiz
Prelims of Kant get Marx 2.0: a general politics quiz
 
How to Add Existing Field in One2Many Tree View in Odoo 17
How to Add Existing Field in One2Many Tree View in Odoo 17How to Add Existing Field in One2Many Tree View in Odoo 17
How to Add Existing Field in One2Many Tree View in Odoo 17
 
Ultra structure and life cycle of Plasmodium.pptx
Ultra structure and life cycle of Plasmodium.pptxUltra structure and life cycle of Plasmodium.pptx
Ultra structure and life cycle of Plasmodium.pptx
 
2024.03.23 What do successful readers do - Sandy Millin for PARK.pptx
2024.03.23 What do successful readers do - Sandy Millin for PARK.pptx2024.03.23 What do successful readers do - Sandy Millin for PARK.pptx
2024.03.23 What do successful readers do - Sandy Millin for PARK.pptx
 
What is the Future of QuickBooks DeskTop?
What is the Future of QuickBooks DeskTop?What is the Future of QuickBooks DeskTop?
What is the Future of QuickBooks DeskTop?
 
Patient Counselling. Definition of patient counseling; steps involved in pati...
Patient Counselling. Definition of patient counseling; steps involved in pati...Patient Counselling. Definition of patient counseling; steps involved in pati...
Patient Counselling. Definition of patient counseling; steps involved in pati...
 
Drug Information Services- DIC and Sources.
Drug Information Services- DIC and Sources.Drug Information Services- DIC and Sources.
Drug Information Services- DIC and Sources.
 
The basics of sentences session 10pptx.pptx
The basics of sentences session 10pptx.pptxThe basics of sentences session 10pptx.pptx
The basics of sentences session 10pptx.pptx
 
General views of Histopathology and step
General views of Histopathology and stepGeneral views of Histopathology and step
General views of Histopathology and step
 
5 charts on South Africa as a source country for international student recrui...
5 charts on South Africa as a source country for international student recrui...5 charts on South Africa as a source country for international student recrui...
5 charts on South Africa as a source country for international student recrui...
 

Nand or gates ver_student

  • 1. KL 2164 DIGITAL ELECTRONICS Multi Level Gate Circuit Pn. Wan Nurdiana Wan Ibrahim nurdiana@eng.ukm.my
  • 2. Multi-Level Gate Circuits Terminology: 1. AND-OR circuit means a two-level circuit composed of a level of AND gates followed by an OR gate at the output. 2. OR-AND circuit means a two-level circuit composed of a level of OR gates followed by an AND gate at the output. 3. OR-AND-OR circuit means a three-level circuit composed of a level of OR gates followed by a level of AND gates followed by an OR gate at the output. 4. Circuit of AND and OR gates implies no particular ordering of the gates; the output gate may be either AND or OR. 2
  • 3. Four-Level Realization of Z Each node on a tree diagram represents a gate, and the number of gate inputs is written beside each node. 3
  • 4. 4
  • 5. Z = (AB + C) (D+ E + FG) + H Number of level? Number of gate? Number of gate input? Change to three levels by partially multiplying it out : Z = (AB + C) (D+ E + FG) + H 5
  • 7. Example Find a circuit of AND and OR gates to realize f (a, b, c, d) = Ʃ m(1, 5, 6, 10, 13, 14)  Consider solutions with two levels of gates and three levels of gates.  Try to minimize the number of gates and the total number of gate inputs.  Assume that all variables and their complements are available as inputs. First, simplify f by using a Karnaugh map. 7
  • 8. 8
  • 9. This leads directly to a two-level AND-OR gate circuit. 9
  • 11. Both of these solutions have an OR gate at the output. A solution with an AND gate at the output might have fewer gates or gate inputs. A two-level OR-AND circuit corresponds to a product-of-sums expression for the function. This can be obtained from the 0′s on the Karnaugh map as follows: f ′ = c′d + ab′c′ + cd + a′b′c leads directly to a two-level OR-AND circuit. 11
  • 12. 12
  • 13. To get a three-level circuit with an AND gate output, we partially multiply out using (X + Y)(X + Z) = X + Y Z: It would require four levels of gates to realize; however, if we multiply out d′(a + b) and d(a′ + b), we get which leads directly to a three-level AND-OR-AND circuit. 13
  • 14. 14
  • 15. For this particular example, the best two-level solution had an AND gate at the output the best three-level solution had an OR gate at the output. In general, to be sure of obtaining a minimum solution, must find both the circuit with the AND-gate output and the one with the OR-gate output. 15
  • 16. NAND gates The small circle (or “bubble”) at the gate output indicates inversion  the NAND gate = AND gate followed by an inverter. The gate output is F = (ABC)′ = A′ + B′ + C′ 16
  • 17. NOR gates Shows a three-input NOR gate. NOR gate = OR gate followed by an inverter. The gate output is F = (A + B + C)′ = A′B′C′ 17
  • 18. Functionally Complete Set of Gates AND and NOT are a functionally complete set of gates because OR can also be realized using AND and NOT: 18
  • 19. NAND Gates Similarly, any function can be realized using only NAND gates: 19
  • 20. Design of Two-Level NAND-Gate Circuits A two-level circuit composed of AND and OR gates is easily converted to a circuit composed of NAND gates or NOR gates Step 1: using F = (F′)′ Step 2 : applying DeMorgan′s laws: (X1 + X2 + … + Xn)′ = X1′ X2′…Xn′ (X1 X2…Xn)′ = X1′ + X2′ + … + Xn′ 20
  • 21. Design of Two-Level NAND-Gate Circuits –cont. Example illustrates conversion of a minimum sum-of-products form to several other two-level forms: F = A + BC′ + B′CD = [(A + BC′ + B′CD)′ ]′ AND-OR = [A′ • (BC′)′ • (B′CD)′]′ NAND-NAND = [A′ • (B′ + C) • (B + C′ + D′)]′ OR-NAND = A + (B′ + C)′ + (B + C′ + D′)′ NOR-OR 21
  • 22. Design of Two-Level NOR-Gate Circuits Want a two-level circuit containing only NOR gates;  start with the minimum product-of-sums form for F. F can be written in the following two-level forms: F = (A + B + C)(A + B′ + C′)(A + C′ + D) OR-AND = {[(A + B + C)(A + B′ + C′)(A + C′ + D)]′ }′ = [(A + B + C)′ + (A + B′ + C′)′ + (A + C′ + D)′]′ NOR-NOR = (A′B′C′ + A′BC + A′CD′)′ AND-NOR = (A′B′C′)′ • (A′BC)′ • (A′CD′)′ NAND-AND 22
  • 23. Eight Basic Forms for Two-Level Circuits 23
  • 24. The other eight possible two-level forms: (AND-AND,OR-OR,OR-NOR,AND-NAND,NAND-NOR,NOR-NAND etc ) degenerate ;cannot realize all switching functions. Consider, for example, the following NAND-NOR circuit: From this example, it is clear that the NAND-NOR form can realize only a product of literals and not a sum of products. 24
  • 25. Design of Minimum Two-Level NAND-NAND Circuits Procedure for designing a minimum two-level NAND-NAND circuit: 1. Find a minimum sum-of-products expression for F. 2. Draw the corresponding two-level AND-OR circuit. 3. Replace all gates with NAND gates leaving the gate interconnection unchanged. If the output gate has any single literals as inputs, complement these literals. 25
  • 26. F = l1 + l2 + • • • + P1 + P2 + • • • F = (l1′l2′ • • • P1′P2′ • • •)′ 26
  • 27. Design of Multi-Level NAND- and NOR-Gate Circuits The following procedure may be used to design multi-level NAND-gate circuits: 1. Simplify the switching function to be realized. 2. Design a multi-level circuit of AND and OR gates. The output gate must be OR. AND gate outputs cannot be used as AND- gate inputs; OR-gate outputs cannot be used as OR-gate inputs. 3. Number the levels starting with the output gate as level 1. Replace all gates with NAND gates, leaving all interconnections between gates unchanged, leave the inputs to levels 2,4,6,… unchanged. Invert any literals which appear as inputs to levels 1,3,5,… 27
  • 28. 28
  • 29. Alternative Gate Symbols Logic designers who design complex digital systems often find it convenient to use more than one representation for a given type of gate. For example, an inverter can be represented by 29
  • 30. Alternative Gate Symbols Equivalent gate symbols based on DeMorgan′s Laws 30
  • 31. NAND Gate Circuit Conversion 31
  • 32. Conversion to NOR Gates 32
  • 33. Conversion of AND-OR Circuit to NAND Gates 33
  • 34. Design of Two-Level, Multiple-Output Circuits Solution of digital design problems often requires the realization of several functions of the same variables. Although each function could be realized separately, the use of some gates in common between two or more functions sometimes leads to a more economical realization. Example: Design a circuit with four inputs and three outputs which realizes the functions 34
  • 35. 35
  • 36. Draw the Circuit Realization 36
  • 37. Multiple-Output Realization of Equations Realization of functions with shared gates (lower overall cost) (7 Gates) 37
  • 38. Another example of sharing gates among multiple outputs to reduce cost. f1 = Ʃ m(2, 3, 5, 7, 8, 9, 10, 11, 13, 15) f2 = Ʃ m(2, 3, 5, 6, 7, 10, 11, 14, 15) f3 = Ʃ m(6, 7, 8, 9, 13, 14, 15) Draw the Karnaugh Map: 38
  • 40. In this example, the best solution is obtained by not combining the circled 1 with adjacent 1’s. 40
  • 41. The solution with the maximum number of common terms is not necessarily the best solution, as illustrated by this example. 41
  • 42. Multi-Level Circuit Conversion to NOR Gates The procedure for design of single- output, multi-level NAND- and NOR- gate circuits also applies to multiple- output circuits 42