Background Swapping Contiguous Memory Allocation Paging Structure of the Page Table Segmentation Example: The Intel Pentium

1. Chapter 8: Main Memory

7. Multistep Processing of a User Program

10. Dynamic relocation using a relocation register

14. Schematic View of Swapping

16. HW address protection with base and limit registers

22. Paging Hardware

23. Paging Model of Logical and Physical Memory

24. Paging Example 32-byte memory and 4-byte pages

25. Free Frames Before allocation After allocation

28. Paging Hardware With TLB

31. Valid (v) or Invalid (i) Bit In A Page Table

33. Shared Pages Example

36. Two-Level Page-Table Scheme

38. Address-Translation Scheme

39. Three-level Paging Scheme

41. Hashed Page Table

43. Inverted Page Table Architecture

45. User’s View of a Program

46. Logical View of Segmentation 1 3 2 4 user space physical memory space 1 4 2 3

49. Segmentation Hardware

50. Example of Segmentation

52. Logical to Physical Address Translation in Pentium

53. Intel Pentium Segmentation

54. Pentium Paging Architecture

55. Linear Address in Linux Broken into four parts:

56. Three-level Paging in Linux

57. End of Chapter 8