1. Porting FreeRTOS on OpenRISC
Speaker：Yi-Chiao Lin

2. • Motivation
• OpenRISC
• Porting FreeRTOS on OpenRISC
• Experiments
Outline

3.  Multi-Tasking Management Support
• Round-Robin 、 FIFO ……
 Memory Management Unit Support
• TLB、Page Table ……
 On-chip Memory Architecture Support
• Cache and SPM (scratch pad memory)
Motivation

4.  Scratch Pad Memory(SPM)
• Software controlled on-chip memory
• Consume less energy than cache
SPM (scratch pad memory)

5. • Motivation
• OpenRISC
• Porting FreeRTOS on OpenRISC
• Experiments
Outline

6.  Or1200 Open Hardware CPU released
 Implemented in the Verilog
 5-stage pipeline
 32 register
Special-Purpose Registers
OpenRISC

7.  l.mfspr / l.mtspr
 MMU、Cache、Interrupt……
OpenRISC
Enable/Disable

8. • Motivation
• OpenRISC
• Porting FreeRTOS on OpenRISC
• Experiments
Outline

9.  Real time operating system
 Designed to be small and simple(2k~3k)
 Stack can be shared between tasks
 For free!!
FreeRTOS benefit

10. Task Create
xTaskCreate(
pdTASK_CODE pvTaskCode,
const portCHAR * const pcName,
unsigned portSHORT usStackDepth,
void *pvParameters,
unsigned portBASE_TYPE uxPriority,
xTaskHandle *pvCreatedTask )

11. void vRtosTask(void *pvParameters){
while(1){
.........
}
}
Task

12. xTaskCreate
prvAllocateTCBAndStack(
usStackDepth, puxStackBuffer
);
prvInitialiseTaskLists();
prvInitialiseTCBVariables( pxNewTCB,
pcName, uxPriority, xRegions,
usStackDepth );
prvAddTaskToReadyQueue( pxNewTC
B );

13. • FreeRTOS porting file :
1. Port.c
2. Portmacro.h
3. Portasm.S
4. Port_spr_def.h(OpenRISC)
(Definition of special-purpose registers)
FreeRTOS/Source/portable/[Platform]
FreeRTOS Porting

14. FreeRTOS Porting
Ported layer
Port.c Portmacro.c Portasm.S Port_spr_def.h
Kernel layer
Application layer
Pagetable.c
TLB-miss ISR
Software(FreeRTOS)
Timer ISR
task.c
Data Moving ISR TLB.c
cache.cInterrupt handler
Reset.S
Hardware(OpenRISC)
SPM Redirector
Page miss
Bookkeeping

15. Port_spr_def.h

16. Portmacro.h
 Define Kernel Type

17.  pxPortInitialiseStack
 vPortDisableInterrupts
 vPortEnableInterrupts
 prvSetupTimerInterrupt
 xPortStartScheduler
port.c

18. port.c (*pxPortInitialiseStack)
PxCode
uTaskSR
r31:0x00000031
r30:0x00000030
r29:0x00000029
.
.
.
High address
Low address

19.  vPortDisableInterrupts
 vPortEnableInterrupts
port.c

20. Exception Handler
Exception type Vector offect[11:0] Example
Reset 0x100 Caused by Software or
Hardware reset
Bus error 0x200
Data Page fault 0x300
Instruction Page fault 0x400
Tick Timer 0x500 Timer interrupt
Alignment 0x600
Illegal Instruction 0x700
External interrupt 0x800 External interrupt asserted
D-TLB miss 0x900 No matching entry in DTLB
I-TLB miss 0xA00 No matching entry in ITLB
Range 0xB00
System call 0xC00
Float Point 0xD00
Trap 0xE00

21.  Exception Program Counter Registers
 Exception Supervision Registers
 Exception Effective Address Register
Exception Register

22.  Maximum timer count of 2^32 clock cycles
Tick Timer
TTMR
TTCR
RISC Clk
Tick INT

23. Tick Timer Mode Register

24. Tick Timer Counter

25.  prvSetupTimerInterrupt
Port.c

26. xPortStartScheduler
Task 1
Task2
Memory
Stack_TCB
Stack_TCB
Setup Timer
Load register
Load TCB

27. • Context Switch
 portSAVE_CONTEXT
 portRESTORE_CONTEXT
Portasm.S
Task1 Task2
Stack_TCB Stack_TCB

28. Portasm.S (Tick Handler)

29.  Reset register
 Set Stack point、Clear BSS
 Reset Cache、MMU、UART
Reset.S(Booting)

30.  OpenRISC Start at 0x100
 Clear general-purpose registers
Reset register

31.  Set Stack Pointer
 Clear BSS
Clear BSS (Block Started by Symbol)

32. • Flush Cache
Data Cache Block Invalidate Register
Cache

33. D-cache 8k 512Line 4word
PPN[31:13] 0x1[12:4] 0x8[3:0]
Physical [31:13]
Physical [31:13]
Physical [31:13]
Physical [31:13]
WORD
WORD
WORD
WORD
WORD
Physical [31:13] V
V
V
V
V
WORD
WORD
WORD
WORD 0
1
2
3
4
5
6
7
2047
0
1
2
3
511
13:212:4

34.  Task address space isolation
 Allow safe sharing of memory among multiple tasks
Why OS need MMU Support?
CPU
Task1
Task2
Virtual
Task 1
Task2
Memory
Physical

35. Page Index Level 1[31:24] Page Offset[12:0]Page Index Level 2[23:13]
0
255
PTE
PTE2
+
0
2047
Physical Page Number Page Offset[12:0]
+
Address

36. Page Table entry
Physical Page Number D A WBC CI CCWOMWRWRREV
 Entry Store in Memory
 Set in Data Translation Lookaside Buffer Translate Registers when
DTLB-MISS

37. TLB miss Handler
TLB MISS
Find the Task
Find Page Table
Set TLB register

38. Exception Effective Address Registers
or1200_except.v
Exception Effective Address Registers

39. DTLB Architecture
Virtial address[19:31] Index[13:18] Offset[12:0]
VPN [19:31] V
VPN [19:31] V
VPN [19:31] V
VPN [19:31] V
PPN [13:31]
PPN [13:31]
PPN[13:31]
PPN [13:31]
PPN [13:31]VPN [19:31] V
Direct mapped
相等
&& V=1
Physical address[13:31] Offset
DTLB miss
DTLB Match Register
DTLB Translate Regidter
EEAR:0x6000
W R W R CI
W R W R CI
W R W R CI
W R W R CI
W R W R CI
Super User
W R W R CI

40. Waveform
DTLB Miss
0x900
Interrupt ->
Dmmu Disable
0x100->0x20000100
Interrupt ->
Dmmu Disable
0x100->0x20000100

41. FreeRTOSConfig.h
Set Total Stack、SYSCLK……

42. • Set Uart Base Address、System CLK……
• Cache size set……
Board.h

43. Modify OpenRISC memory architecture
CPU
D-MMU
Data ram
Wishbone bus
Redirector
D-CacheSPM
Page miss
Bookkeeping
circuit
Interrupt

44. PIC (Programmable Interrupt Controller)
Page miss
Bookkeeping
circuit
or1200_cpu.vexternal_interrupt.v
or1200_pic.v
spr_cs
spr_we
spr_addr
spr_dat_i
intr
spr_dat_o
clk
rst
pic_int[31:0]

45. SPM data moving interrupt handler
Free SPM
space?
Interrupt
Select a victim page and
move it to Data ram
Move the page into SPM
No
Yes
Update D-TLB
Translate Regidter
Update Page table

46. • Motivation
• OpenRISC
• Porting FreeRTOS on OpenRISC
• Experiments
Outline

47. Verify on FPGA Board

48. Verify on FPGA Board
VeriComm
Dump Counter

49.  學習移植OS與底層硬體的整合
 善加運用身邊工具Debug
 更加了解CPU之運作
Summary

50. Thank You for Listening
Contact us.
E-mail : joe21013@hotmail.com