Chip Ex2010 Gert Goossens

Design of Programmable Accelerators for SoCs Gert Goossens CEO Target Compiler Technologies

Abstract ,[object Object],[object Object]

Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

[object Object],[object Object],[object Object],[object Object],[object Object],SoC Design

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],SoC Design

How to Design ASIPs? ,[object Object]

How to Design ASIPs? Design step Benefits ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

How to Design ASIPs? ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Tool Comparison ,[object Object],[object Object],[object Object],[object Object],Architectural style Example vendors Approach Yes High Yes EDA license Flexible, using processor description language Target (IP Designer), CoWare (Processor Designer) Retargetable ASIP design tools Yes Low (within template boundaries) Yes Royalties Configurable ASIP template + extension instructions Tensilica, ARC, ASIP Solutions, SiliconHive Configurable ASIP templates No High Depends on tool EDA license Hardwired datapath, no programmability Mentor (CatapultC), Forte, Synfora, Cadence (C2S) High-level synthesis from C — (*) (*) No strong focus for CoWare?

Programmable Datapath Examples  Examples shown  Served by IP Designer

What is a Programmable Datapath? ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],SEQ PM DEC s 0 s 1 s 2 d+=(a+b)*c; g+=(e-f)*f;

Prog. Datapath Example: WLAN ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Matrix inversion Matrix inversion + Address computations Address computations Complex conjugate Square modulus [1] Medea+ project “Uppermost”

[object Object],[object Object],[object Object],[object Object],Prog. Datapath Example: WLAN Dual Port Memory Common Program Control GMAC 0 Dual Port Memory GMAC 1 Dual Port Memory GMAC 2 Dual Port Memory GMAC 3 Channel Estimation ASIP GMAC

Prog. Datapath Example: WLAN ,[object Object],reg R[8] <vcmpl> read(tR0, tR1, tR2, tR3, tR4, tR5); reg ACC <vcmpl>; pipe P0 <vcmpl>; pipe P1 <vcmpl>; trn tC0 <vcmpl>; trn tC1 <vcmpl>; trn tM0 <vcmpl>; trn tM1 <vcmpl>; enum gmac_op {mpy_mpy_mac, mac, sq_sq_mac, minv, ...}; opn gmac(g:gmac_op, r0:c3, r1:c3, r2:c3, r3:c3, r4:c3, r5:c3) { action { stage E1: switch (g) { case mpy_mpy_mac: tC0 = ccnj(tR2 = R[r2]); P0 = cmpy(tR1 = R[r1], tC0); tC1 = ccnj(tR3 = R[r3]); P1 = cmpy(tR4 = R[r4], tC1 ); case mac: P0 = tR0 = R[r0]; P1 = tR5 = R[r5]; case sq_sq_mac: P0 = cmpy(tR1 = R[r1], tR2 = R[r1]); P1 = cmpy(tR4 = R[r4], tR3 = R[r4]); case minv: P0 = tR0 = R[r0]; tM0 = cmpy(tR1 = R[r1], tR2 = R[r2]); tM1 = cmpy(tR4 = R[r4], tR3 = R[r3]); P1 = csub(tM0, tM1); case ... } stage E2: tM = cmpy(P0, P1); ACC = cadd(tM, ACC); } }  Resources Instruction-set  grammar

Prog. Datapath Example: WLAN ,[object Object],COMPILATION ENGINE (PHASE COUPLING) Application C Machine code Elf / Dwarf Processor model nML ISG sub_AB sub_BA add_AB add_BA A B C <<_C AR_w CDFG + << nML FRONT-END C FRONT-END SOURCE-LEVEL TRANSF. CODE SELECTION REGISTER ALLOCATION SCHEDULING CODE EMISSION

Prog. Datapath Example: FFT ,[object Object],[object Object],[object Object],[object Object],[object Object]

Prog. Datapath Example: FFT ,[object Object],[object Object],[object Object],[object Object],Mdata Mcoef A[4] B[4] CMPY BFLY ld A/B Ld C stA/B * * * * - + + + - -

Prog. Datapath Example: FFT ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],/* 0 */ DO cnt,LE /* 1 */ /* delay slot */ /* 2 */ md=*pa(next_bfly) | *pb(+s)=b1 | mc=*pr(next_bfly_rdx4) | a2=md*mc | b3,b2=bfly(a2,a3) /* 3 */ md=*pa(+s) | *pb(+s)=b3 | mc=*pr(+s) | a3=md*mc | b1,a2=bfly(a1,a2) /* 4 */ md=*pa(+s) | *pb(+s)=b0 | mc=*pr(+s) | a1=md*mc | b0,a3=bfly(a0,a3) /* 5 */ md=*pa(+s) | *pb(next_bfly)=b2 | mc=*pr(+s) |a0=md*mc | b1,b0=bfly(b1,b0) LDA LDC MPY LDA LDC MPY LDA LDC MPY LDA LDC MPY BFLY BFLY BFLY BFLY STB STB STB STB LDA STB LDC MPY BFLY

Prog. Datapath Example: FFT ,[object Object],[object Object],[object Object],[object Object],COMPILATION ENGINE (PHASE COUPLING) Application C Machine code Elf / Dwarf Processor model nML ISG sub_AB sub_BA add_AB add_BA A B C <<_C AR_w CDFG + << nML FRONT-END C FRONT-END SOURCE-LEVEL TRANSF. CODE SELECTION REGISTER ALLOCATION SCHEDULING CODE EMISSION

Prog. Datapath Example: FFT ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Conclusion ,[object Object],[object Object],[object Object],[object Object],[object Object]

Chip Ex2010 Gert Goossens

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