1. VHDL 360© by: Amr Ali

2. Copyrights Copyright © 2010 to authors. All rights reserved All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Amr Ali or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws. Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses. Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners. VHDL 360 © 2

3. Objective Using ModelSim to compile and simulate a given design unit Skills gained: Identify basic Simulator commands VHDL 360 © 3

4. Outline Command Line Simulation Compile and Simulate Add Signals to Wave Applying Inputs Interactive Simulation VHDL 360 © 4

5. Command Line Simulation Make sure Modelsim exists in the path by doing the following Windows: Start run -> cmd In cmd window: vsim -version Linux: In any shell: vsim -version VHDL 360 © 5

6. Command Line Simulation Create VHDL file Edit the file my_demo1.vhd Insert the text and save VHDL 360 © 6 LIBRARYieee; USEieee.std_logic_1164.all; ENTITYandgateIS port(a, b:instd_logic_vector(2downto0); c:outstd_logic_vector(2downto0)); ENDENTITY; ARCHITECTUREbehavOFandgateIS BEGIN c <= a and b; ENDARCHITECTURE;

8. vcom: compiles VHDL files, the files should be ordered in a hierarchal way [leaf level first then top]

12. Make Files On Unix: If you changed the code you will have to recompile the design files again. A make file is used to do repetitive compilation and simulation tasks; “Make” knows which files have been edited and automatically compiles only changed files. ModelSim offers a simple way to automatically generate a Makefile for your design hierarchy. vmake work > Makefile To recompile code at anytime just type make VHDL 360 © 11

13. Interactive Simulation File  new project Insert project name and location; leave other fields with defaults VHDL 360 © 12

14. Interactive Simulation In “Add items to the project” window choose “Create new file” Insert file name Make sure to select VHDL VHDL 360 © 13

15. Interactive Simulation Create VHDL file Edit the file my_demo1.vhd Insert the text and save VHDL 360 © 14 LIBRARYieee; USEieee.std_logic_1164.all; ENTITYandgateIS port(a, b:instd_logic_vector(2downto0); c:outstd_logic_vector(2downto0)); ENDENTITY; ARCHITECTUREbehavOFandgateIS BEGIN c <= a and b; ENDARCHITECTURE;

16. Compile VHDL files Select the file  RMB  compile selected VHDL 360 © 15

17. Simulation Simulate menu  Start Simulation Expand work library and select andgateOK VHDL 360 © 16

18. Contacts You can contact us at: http://www.embedded-tips.blogspot.com/ VHDL 360 © 17