SlideShare une entreprise Scribd logo
1  sur  22
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
Lecture 8: Sequential Logic
Latches & Flip-flops
 Introduction
 Memory Elements
 Pulse-Triggered Latch
S-R Latch
 Edge-Triggered Flip-flops
S-R Flip-flop
D Flip-flop
J-K Flip-flop
T Flip-flop
CS1104-11 1
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
Introduction
 A sequential circuit consists of a feedback
path, and employs some memory elements.
CS1104-11 Introduction 2
Combinational
logic
Memory
elements
Combinational
outputs Memory outputs
External inputs
Sequential circuit = Combinational logic + Memory Elements
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
Introduction
 There are two types of sequential circuits:
 synchronous: outputs change only at specific time
 asynchronous: outputs change at any time
Multivibrator: a class of sequential circuits. They can
be:
 bistable (2 stable states)
 monostable or one-shot (1 stable state)
 astable (no stable state)
 Bistable logic devices: latches and flip-flops.
 Latches and flip-flops differ in the method used
for changing their state.
CS1104-11 Introduction 3
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
Memory Elements
 Memory element with clock. Flip-flops are
memory elements that change state on
clock signals.
 Clock is usually a square wave.
CS1104-11 Memory Elements 4
command
Memory
element stored value
Q
clock
Positive edges Negative edges
Positive pulses
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
Memory Elements
 Two types of triggering/activation:
 pulse-triggered
 edge-triggered
 Pulse-triggered
 latches
 ON = 1, OFF = 0
 Edge-triggered
 flip-flops
 positive edge-triggered (ON = from 0 to 1; OFF = other
time)
 negative edge-triggered (ON = from 1 to 0; OFF =
other time)CS1104-11 Memory Elements 5
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
S-R Latch Complementary outputs: Q and Q'.
 When Q is HIGH, the latch is in SET state.
 When Q is LOW, the latch is in RESET
state.
 For active-HIGH input S-R latch (also known as
NOR gate latch),
R=HIGH (and S=LOW) a RESET state
S=HIGH (and R=LOW) a SET state
both inputs LOW a no change
both inputs HIGH a Q and Q' both LOW (invalid)!
CS1104-11 S-R Latch 6
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
S-R Latch
 For active-LOW input S'-R' latch (also known as
NAND gate latch),
R'=LOW (and S'=HIGH) a RESET state
S'=LOW (and R'=HIGH) a SET state
both inputs HIGH a no change
both inputs LOW a Q and Q' both HIGH (invalid)!
 Drawback of S-R latch: invalid condition
exists and must be avoided.
CS1104-11 S-R Latch 7
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
S-R Latch
 Characteristics table for active-high input
S-R latch:
 Characteristics table for active-low input S'-
R' latch:
CS1104-11
S-R Latch
8
S R Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
S' R' Q Q'
1 1 NC NC No change. Latch
remained in present state.
0 1 1 0 Latch SET.
1 0 0 1 Latch RESET.
0 0 1 1 Invalid condition.
S
R
Q
Q'
S
R
Q
Q'
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
S-R Latch
 Active-HIGH input S-R latch
 Active-LOW input S’-R’ latch
CS1104-11 S-R Latch 9
R
S
Q
Q'
S R Q Q'
1 0 1 0 initial
0 0 1 0 (afer S=1, R=0)
0 1 0 1
0 0 0 1 (after S=0, R=1)
1 1 0 0 invalid!
S' R' Q Q'
1 0 0 1 initial
1 1 0 1 (afer S'=1, R'=0)
0 1 1 0
1 1 1 0 (after S'=0, R'=1)
0 0 1 1 invalid!
S'
R'
Q
Q'
S'
R'
Q
Q'
0
1
1
0
0
0
1
0
1
0
0
1
0
0
0
1
1
1
0
0
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
J-K Flip-flop
 J-K flip-flop: Q and Q' are fed back to the
pulse-steering NAND gates.
 No invalid state.
 Include a toggle state.
J=HIGH (and K=LOW) a SET state
K=HIGH (and J=LOW) a RESET state
both inputs LOW a no change
both inputs HIGH a toggle
CS1104-11 J-K Flip-Ffop 10
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
J-K Flip-flop J-K flip-flop.
 Characteristic table.
CS1104-11 J-K Flip-flop 11
J
Q
Q'
CLK
Pulse
transition
detector
K
J K CLK Q(t+1) Comments
0 0  Q(t) No change
0 1  0 Reset
1 0  1 Set
1 1  Q(t)' Toggle
Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Q(t+1) = J.Q' + K'.Q
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3Memory
Main memory consists of a number of
storage locations, each of which is
identified by a unique address
The ability of the CPU to identify each
location is known as its addressability
Each location stores a word i.e. the
number of bits that can be processed
by the CPU in a single operation. Word
length may be typically 16, 24, 32 or
as many as 64 bits.
A large word length improves system
performance, though may be less
efficient on occasions when the full
word length is not used
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
Calculating the Maximum Capacity of
Memory in a Computer
• Max capacity =
• number of address x capacity of each location
Example
What is the maximum amount of memory in a system which has a
16 bit data bus and a 24 bit address bus?
Answer
224 x 2
16777216 x 2
33554432 bytes
32768 Kb
32Mb
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3Types of main memory
There are two types of main memory, Random Access Memory
(RAM) and Read Only Memory (ROM)
Random Access Memory (RAM)
holds its data as long as the computer is switched on
All data in RAM is lost when the computer is switched off
Described as being volatile
It is direct access as it can be both written to or read from in
any order
Its purpose is to temporarily hold programs and data for
processing. In modern computers it also holds the operating
system
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
Types of RAM
1. Dynamic Random Access Memory (DRAM)
• Contents are constantly refreshed 1000 times per second
• Access time 60 – 70 nanoseconds
Note: a nanosecond is one billionth of a second!
2. Synchronous Dynamic Random Access Memory
(SDRAM)
• Quicker than DRAM
• Access time less than 60 nanoseconds
3. Direct Rambus Dynamic Random Access Memory
(DRDRAM)
• New type of RAM architecture
• Access time 20 times faster than DRAM
• More expensive
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
4. Static Random Access Memory (SRAM)
• Doesn’t need refreshing
• Retains contents as long as power applied to the chip
• Access time around 10 nanoseconds
• Used for cache memory
• Also for date and time settings as powered by small battery
5. Cache memory
• Small amount of memory typically 256 or 512 kilobytes
• Temporary store for often used instructions
• Level 1 cache is built within the CPU (internal)
• Level 2 cache may be on chip or nearby (external)
• Faster for CPU to access than main memory
Types of RAM
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
The operation of cache memory
1. Cache fetches
data from next to
current addresses
in main memory
2. CPU checks to
see whether the
next instruction it
requires is in cache
3. If it is, then
the instruction is
fetched from the
cache – a very fast
position
4. If not, the CPU
has to fetch next
instruction from
main memory - a
much slower process
Main
Memory
(DRAM)
CPU
Cache
Memory
(SRAM)
= Bus connections
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3Types of RAM
6. Virtual memory
• Uses backing storage e.g. hard disk as a temporary location
for programs and data where insufficient RAM available
• Swaps programs and data between the hard-disk and RAM as
the CPU requires them for processing
• A cheap method of running large or many programs on a
computer system
• Cost is speed: the CPU can access RAM in nanoseconds but
hard-disk in milliseconds (Note: a millisecond is a thousandth
of a second)
• Virtual memory is much slower than RAM
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3Read only memory (ROM)
ROM holds programs and data permanently even when computer is
switched off
Data can be read by the CPU in any order so ROM is also direct
access
The contents of ROM are fixed at the time of manufacture
Stores a program called the bootstrap loader that helps start up
the computer
Access time of between 10 and 50 nanoseconds
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
Types of ROM
1. Programmable Read Only Memory (PROM)
• Empty of data when manufactured
• May be permanently programmed by the user
2. Erasable Programmable Read Only Memory (EPROM)
• Can be programmed, erased and reprogrammed
• The EPROM chip has a small window on top allowing it to be
erased by shining ultra-violet light on it
• After reprogramming the window is covered to prevent new
contents being erased
• Access time is around 45 – 90 nanoseconds
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3Types of ROM
3. Electrically Erasable Programmable Read Only Memory (EEPROM)
• Reprogrammed electrically without using ultraviolet light
• Must be removed from the computer and placed in a special machine to do this
• Access times between 45 and 200 nanoseconds
4. Flash ROM
• Similar to EEPROM
• However, can be reprogrammed while still in the computer
• Easier to upgrade programs stored in Flash ROM
• Used to store programs in devices e.g. modems
• Access time is around 45 – 90 nanoseconds
5. ROM cartridges
• Commonly used in games machines
• Prevents software from being easily copied
Subject Name Code Credit Hours
Digital Electronics and Logic Design DEL-244 3
End of segment

Contenu connexe

Tendances

All About Decoders DLD.
All About Decoders DLD.All About Decoders DLD.
All About Decoders DLD.Zain Jafri
 
Solutions manual for logic and computer design fundamentals 5th edition by ma...
Solutions manual for logic and computer design fundamentals 5th edition by ma...Solutions manual for logic and computer design fundamentals 5th edition by ma...
Solutions manual for logic and computer design fundamentals 5th edition by ma...Beckham000
 
Lab 2-Simple Combinational Logic
Lab 2-Simple Combinational LogicLab 2-Simple Combinational Logic
Lab 2-Simple Combinational LogicKatrina Little
 
Flipflops and Excitation tables of flipflops
Flipflops and Excitation tables of flipflopsFlipflops and Excitation tables of flipflops
Flipflops and Excitation tables of flipflopsstudent
 
Digital Logic & Computer Architecture Practical Book by Yasir Ahmed Khan
Digital Logic & Computer Architecture Practical Book by Yasir Ahmed KhanDigital Logic & Computer Architecture Practical Book by Yasir Ahmed Khan
Digital Logic & Computer Architecture Practical Book by Yasir Ahmed KhanYasir Khan
 
Regular expressions-Theory of computation
Regular expressions-Theory of computationRegular expressions-Theory of computation
Regular expressions-Theory of computationBipul Roy Bpl
 
Panasonic OLED-Training Manual 2020.pdf
Panasonic OLED-Training Manual 2020.pdfPanasonic OLED-Training Manual 2020.pdf
Panasonic OLED-Training Manual 2020.pdfShahidAziz49
 
Presentation on Flip Flop
Presentation  on Flip FlopPresentation  on Flip Flop
Presentation on Flip FlopNahian Ahmed
 
flip flop circuits and its applications
flip flop circuits and its applicationsflip flop circuits and its applications
flip flop circuits and its applicationsGaditek
 
Sequential Logic Circuit
Sequential Logic CircuitSequential Logic Circuit
Sequential Logic CircuitRamasubbu .P
 
Nand and nor as a universal gates
Nand and nor as a universal gatesNand and nor as a universal gates
Nand and nor as a universal gatesKaushal Shah
 
Dot Matrix LED Interfacing using 8255 PPI
Dot Matrix LED Interfacing using 8255 PPIDot Matrix LED Interfacing using 8255 PPI
Dot Matrix LED Interfacing using 8255 PPIAmit Kumer Podder
 

Tendances (20)

Introduction to 8085 by adi ppt
Introduction to 8085 by adi pptIntroduction to 8085 by adi ppt
Introduction to 8085 by adi ppt
 
Triggering devices
Triggering devicesTriggering devices
Triggering devices
 
All About Decoders DLD.
All About Decoders DLD.All About Decoders DLD.
All About Decoders DLD.
 
JK flip flops
JK flip flopsJK flip flops
JK flip flops
 
Solutions manual for logic and computer design fundamentals 5th edition by ma...
Solutions manual for logic and computer design fundamentals 5th edition by ma...Solutions manual for logic and computer design fundamentals 5th edition by ma...
Solutions manual for logic and computer design fundamentals 5th edition by ma...
 
Lab 2-Simple Combinational Logic
Lab 2-Simple Combinational LogicLab 2-Simple Combinational Logic
Lab 2-Simple Combinational Logic
 
Logic gates
Logic gatesLogic gates
Logic gates
 
Flipflops and Excitation tables of flipflops
Flipflops and Excitation tables of flipflopsFlipflops and Excitation tables of flipflops
Flipflops and Excitation tables of flipflops
 
Digital Logic & Computer Architecture Practical Book by Yasir Ahmed Khan
Digital Logic & Computer Architecture Practical Book by Yasir Ahmed KhanDigital Logic & Computer Architecture Practical Book by Yasir Ahmed Khan
Digital Logic & Computer Architecture Practical Book by Yasir Ahmed Khan
 
Regular expressions-Theory of computation
Regular expressions-Theory of computationRegular expressions-Theory of computation
Regular expressions-Theory of computation
 
Registers
RegistersRegisters
Registers
 
Panasonic OLED-Training Manual 2020.pdf
Panasonic OLED-Training Manual 2020.pdfPanasonic OLED-Training Manual 2020.pdf
Panasonic OLED-Training Manual 2020.pdf
 
Latches and flip flops
Latches and flip flopsLatches and flip flops
Latches and flip flops
 
Memory Reference instruction
Memory Reference instructionMemory Reference instruction
Memory Reference instruction
 
Presentation on Flip Flop
Presentation  on Flip FlopPresentation  on Flip Flop
Presentation on Flip Flop
 
flip flop circuits and its applications
flip flop circuits and its applicationsflip flop circuits and its applications
flip flop circuits and its applications
 
Sequential Logic Circuit
Sequential Logic CircuitSequential Logic Circuit
Sequential Logic Circuit
 
Nand and nor as a universal gates
Nand and nor as a universal gatesNand and nor as a universal gates
Nand and nor as a universal gates
 
Dot Matrix LED Interfacing using 8255 PPI
Dot Matrix LED Interfacing using 8255 PPIDot Matrix LED Interfacing using 8255 PPI
Dot Matrix LED Interfacing using 8255 PPI
 
Logic gates presentation
Logic gates presentationLogic gates presentation
Logic gates presentation
 

En vedette

Read Only Memory
Read Only Memory Read Only Memory
Read Only Memory rohitladdu
 
Chap iii-Logic Gates
Chap iii-Logic GatesChap iii-Logic Gates
Chap iii-Logic GatesBala Ganesh
 
Chap ii.BCD code,Gray code
Chap ii.BCD code,Gray codeChap ii.BCD code,Gray code
Chap ii.BCD code,Gray codeBala Ganesh
 
Flip flop’s state tables & diagrams
Flip flop’s state tables & diagramsFlip flop’s state tables & diagrams
Flip flop’s state tables & diagramsSunny Khatana
 
RAM and ROM Memory Overview
RAM and ROM Memory OverviewRAM and ROM Memory Overview
RAM and ROM Memory OverviewPankaj Khodifad
 
Advanced Rotating Machines - Mike Werst
Advanced Rotating Machines - Mike WerstAdvanced Rotating Machines - Mike Werst
Advanced Rotating Machines - Mike Werstcahouser
 
Grid energy storage
Grid energy storageGrid energy storage
Grid energy storageMd Raheel
 
Difference between combinational and
Difference between combinational andDifference between combinational and
Difference between combinational andDamodar Panigrahy
 
power generation through speed breaker
power generation through speed breakerpower generation through speed breaker
power generation through speed breakerShifa Nadeem
 
Energy Generation from road speed breaker
Energy Generation from road speed breakerEnergy Generation from road speed breaker
Energy Generation from road speed breakerparikshitpurandare
 

En vedette (20)

Read Only Memory
Read Only Memory Read Only Memory
Read Only Memory
 
karnaugh maps
karnaugh mapskarnaugh maps
karnaugh maps
 
Chap iii-Logic Gates
Chap iii-Logic GatesChap iii-Logic Gates
Chap iii-Logic Gates
 
DEL-244Chep i
DEL-244Chep iDEL-244Chep i
DEL-244Chep i
 
Chap ii.BCD code,Gray code
Chap ii.BCD code,Gray codeChap ii.BCD code,Gray code
Chap ii.BCD code,Gray code
 
Flip flop’s state tables & diagrams
Flip flop’s state tables & diagramsFlip flop’s state tables & diagrams
Flip flop’s state tables & diagrams
 
RAM and ROM Memory Overview
RAM and ROM Memory OverviewRAM and ROM Memory Overview
RAM and ROM Memory Overview
 
Advanced Rotating Machines - Mike Werst
Advanced Rotating Machines - Mike WerstAdvanced Rotating Machines - Mike Werst
Advanced Rotating Machines - Mike Werst
 
Grid energy storage
Grid energy storageGrid energy storage
Grid energy storage
 
Difference between combinational and
Difference between combinational andDifference between combinational and
Difference between combinational and
 
Short Channel Effect In MOSFET
Short Channel Effect In MOSFETShort Channel Effect In MOSFET
Short Channel Effect In MOSFET
 
As jatav...ppt on vibration
As jatav...ppt on vibrationAs jatav...ppt on vibration
As jatav...ppt on vibration
 
Lec microwave
Lec microwaveLec microwave
Lec microwave
 
Magnetron
MagnetronMagnetron
Magnetron
 
GYROBUS
GYROBUSGYROBUS
GYROBUS
 
Flywheels- An Alternative Energy Storage Method
Flywheels- An Alternative Energy Storage MethodFlywheels- An Alternative Energy Storage Method
Flywheels- An Alternative Energy Storage Method
 
Digital design chap 5
Digital design   chap 5Digital design   chap 5
Digital design chap 5
 
power generation through speed breaker
power generation through speed breakerpower generation through speed breaker
power generation through speed breaker
 
Energy Generation from road speed breaker
Energy Generation from road speed breakerEnergy Generation from road speed breaker
Energy Generation from road speed breaker
 
STLD-Combinational logic design
STLD-Combinational  logic design STLD-Combinational  logic design
STLD-Combinational logic design
 

Similaire à Flip flop& RAM ROM

EC8392 -DIGITAL ELECTRONICS -II YEAR ECE-by S.SESHA VIDHYA /ASP/ ECE/ RMKCET
EC8392 -DIGITAL ELECTRONICS -II YEAR ECE-by S.SESHA VIDHYA /ASP/ ECE/ RMKCETEC8392 -DIGITAL ELECTRONICS -II YEAR ECE-by S.SESHA VIDHYA /ASP/ ECE/ RMKCET
EC8392 -DIGITAL ELECTRONICS -II YEAR ECE-by S.SESHA VIDHYA /ASP/ ECE/ RMKCETSeshaVidhyaS
 
System design using HDL - Module 3
System design using HDL - Module 3System design using HDL - Module 3
System design using HDL - Module 3Aravinda Koithyar
 
W8_1: Intro to UoS Educational Processor
W8_1: Intro to UoS Educational ProcessorW8_1: Intro to UoS Educational Processor
W8_1: Intro to UoS Educational ProcessorDaniel Roggen
 
Digital Electronics – Unit V.pdf
Digital Electronics – Unit V.pdfDigital Electronics – Unit V.pdf
Digital Electronics – Unit V.pdfKannan Kanagaraj
 
UNIT 3 - General Purpose Processors
UNIT 3 - General Purpose ProcessorsUNIT 3 - General Purpose Processors
UNIT 3 - General Purpose ProcessorsButtaRajasekhar2
 
Lec13 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Multicore
Lec13 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- MulticoreLec13 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Multicore
Lec13 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- MulticoreHsien-Hsin Sean Lee, Ph.D.
 
Basic Computer Architecture
Basic Computer ArchitectureBasic Computer Architecture
Basic Computer ArchitectureYong Heui Cho
 
Introduction to Computer Architecture and Organization
Introduction to Computer Architecture and OrganizationIntroduction to Computer Architecture and Organization
Introduction to Computer Architecture and OrganizationDr. Balaji Ganesh Rajagopal
 
Integrating Cache Oblivious Approach with Modern Processor Architecture: The ...
Integrating Cache Oblivious Approach with Modern Processor Architecture: The ...Integrating Cache Oblivious Approach with Modern Processor Architecture: The ...
Integrating Cache Oblivious Approach with Modern Processor Architecture: The ...Tokyo Institute of Technology
 
Scan Based Side Channel Attack on Data Encryption Standard
Scan Based Side Channel Attack on Data Encryption StandardScan Based Side Channel Attack on Data Encryption Standard
Scan Based Side Channel Attack on Data Encryption StandardLei Hsiung
 
ASTROSAT SSR - 2015-05-15
ASTROSAT SSR - 2015-05-15ASTROSAT SSR - 2015-05-15
ASTROSAT SSR - 2015-05-15Aritra Sarkar
 
Lec11 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Memory part3
Lec11 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Memory part3Lec11 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Memory part3
Lec11 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Memory part3Hsien-Hsin Sean Lee, Ph.D.
 
Beneath the Linux Interrupt handling
Beneath the Linux Interrupt handlingBeneath the Linux Interrupt handling
Beneath the Linux Interrupt handlingBhoomil Chavda
 
Embedded Systems,Embedded Systems Project,Winter training,
Embedded Systems,Embedded Systems Project,Winter training,Embedded Systems,Embedded Systems Project,Winter training,
Embedded Systems,Embedded Systems Project,Winter training,Technogroovy
 
PPT of Dr. Arun Somani_MIPS_SC-Extended.pdf
PPT of Dr. Arun Somani_MIPS_SC-Extended.pdfPPT of Dr. Arun Somani_MIPS_SC-Extended.pdf
PPT of Dr. Arun Somani_MIPS_SC-Extended.pdfUsssshaaaMehta
 
Unit v memory & programmable logic devices
Unit v   memory & programmable logic devicesUnit v   memory & programmable logic devices
Unit v memory & programmable logic devicesKanmaniRajamanickam
 
6 open capi_meetup_in_japan_final
6 open capi_meetup_in_japan_final6 open capi_meetup_in_japan_final
6 open capi_meetup_in_japan_finalYutaka Kawai
 
microcontroller 8051 17.07.2023.pdf
microcontroller 8051 17.07.2023.pdfmicrocontroller 8051 17.07.2023.pdf
microcontroller 8051 17.07.2023.pdf818Farida
 

Similaire à Flip flop& RAM ROM (20)

EC8392 -DIGITAL ELECTRONICS -II YEAR ECE-by S.SESHA VIDHYA /ASP/ ECE/ RMKCET
EC8392 -DIGITAL ELECTRONICS -II YEAR ECE-by S.SESHA VIDHYA /ASP/ ECE/ RMKCETEC8392 -DIGITAL ELECTRONICS -II YEAR ECE-by S.SESHA VIDHYA /ASP/ ECE/ RMKCET
EC8392 -DIGITAL ELECTRONICS -II YEAR ECE-by S.SESHA VIDHYA /ASP/ ECE/ RMKCET
 
System design using HDL - Module 3
System design using HDL - Module 3System design using HDL - Module 3
System design using HDL - Module 3
 
W8_1: Intro to UoS Educational Processor
W8_1: Intro to UoS Educational ProcessorW8_1: Intro to UoS Educational Processor
W8_1: Intro to UoS Educational Processor
 
Digital Electronics – Unit V.pdf
Digital Electronics – Unit V.pdfDigital Electronics – Unit V.pdf
Digital Electronics – Unit V.pdf
 
UNIT 3 - General Purpose Processors
UNIT 3 - General Purpose ProcessorsUNIT 3 - General Purpose Processors
UNIT 3 - General Purpose Processors
 
Lec13 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Multicore
Lec13 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- MulticoreLec13 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Multicore
Lec13 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Multicore
 
Basic Computer Architecture
Basic Computer ArchitectureBasic Computer Architecture
Basic Computer Architecture
 
Introduction to Computer Architecture and Organization
Introduction to Computer Architecture and OrganizationIntroduction to Computer Architecture and Organization
Introduction to Computer Architecture and Organization
 
Integrating Cache Oblivious Approach with Modern Processor Architecture: The ...
Integrating Cache Oblivious Approach with Modern Processor Architecture: The ...Integrating Cache Oblivious Approach with Modern Processor Architecture: The ...
Integrating Cache Oblivious Approach with Modern Processor Architecture: The ...
 
Scan Based Side Channel Attack on Data Encryption Standard
Scan Based Side Channel Attack on Data Encryption StandardScan Based Side Channel Attack on Data Encryption Standard
Scan Based Side Channel Attack on Data Encryption Standard
 
ASTROSAT SSR - 2015-05-15
ASTROSAT SSR - 2015-05-15ASTROSAT SSR - 2015-05-15
ASTROSAT SSR - 2015-05-15
 
Lec11 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Memory part3
Lec11 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Memory part3Lec11 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Memory part3
Lec11 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Memory part3
 
Beneath the Linux Interrupt handling
Beneath the Linux Interrupt handlingBeneath the Linux Interrupt handling
Beneath the Linux Interrupt handling
 
Embedded Systems,Embedded Systems Project,Winter training,
Embedded Systems,Embedded Systems Project,Winter training,Embedded Systems,Embedded Systems Project,Winter training,
Embedded Systems,Embedded Systems Project,Winter training,
 
PPT of Dr. Arun Somani_MIPS_SC-Extended.pdf
PPT of Dr. Arun Somani_MIPS_SC-Extended.pdfPPT of Dr. Arun Somani_MIPS_SC-Extended.pdf
PPT of Dr. Arun Somani_MIPS_SC-Extended.pdf
 
Unit v memory & programmable logic devices
Unit v   memory & programmable logic devicesUnit v   memory & programmable logic devices
Unit v memory & programmable logic devices
 
6 open capi_meetup_in_japan_final
6 open capi_meetup_in_japan_final6 open capi_meetup_in_japan_final
6 open capi_meetup_in_japan_final
 
Chap 02[1]
Chap 02[1]Chap 02[1]
Chap 02[1]
 
microcontroller 8051 17.07.2023.pdf
microcontroller 8051 17.07.2023.pdfmicrocontroller 8051 17.07.2023.pdf
microcontroller 8051 17.07.2023.pdf
 
Patt patelch04
Patt patelch04Patt patelch04
Patt patelch04
 

Plus de Bala Ganesh

Plus de Bala Ganesh (20)

DDL,DML,1stNF
DDL,DML,1stNFDDL,DML,1stNF
DDL,DML,1stNF
 
sfdfds
sfdfdssfdfds
sfdfds
 
Dbms chapter viii
Dbms chapter viiiDbms chapter viii
Dbms chapter viii
 
Dbms chapter vii
Dbms chapter viiDbms chapter vii
Dbms chapter vii
 
Dbms chapter v
Dbms chapter vDbms chapter v
Dbms chapter v
 
Dbms chapter iv
Dbms chapter ivDbms chapter iv
Dbms chapter iv
 
Dbms chapter iii
Dbms chapter iiiDbms chapter iii
Dbms chapter iii
 
Dmbs chapter vi
Dmbs chapter viDmbs chapter vi
Dmbs chapter vi
 
Dbms chapter ii
Dbms chapter iiDbms chapter ii
Dbms chapter ii
 
Dbms chap i
Dbms chap iDbms chap i
Dbms chap i
 
Software engineering Questions and Answers
Software engineering Questions and AnswersSoftware engineering Questions and Answers
Software engineering Questions and Answers
 
Software testing
Software testingSoftware testing
Software testing
 
Design
DesignDesign
Design
 
Comp 107 cep 8
Comp 107 cep 8Comp 107 cep 8
Comp 107 cep 8
 
Comp 107 cep 7
Comp 107 cep 7Comp 107 cep 7
Comp 107 cep 7
 
Cocomo model
Cocomo modelCocomo model
Cocomo model
 
Software Requirements
Software RequirementsSoftware Requirements
Software Requirements
 
Comp107 chep6
Comp107 chep6Comp107 chep6
Comp107 chep6
 
Comp 111chp iv vi
Comp 111chp iv viComp 111chp iv vi
Comp 111chp iv vi
 
Comp 111 cep ii
Comp 111 cep iiComp 111 cep ii
Comp 111 cep ii
 

Dernier

Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)eniolaolutunde
 
Student login on Anyboli platform.helpin
Student login on Anyboli platform.helpinStudent login on Anyboli platform.helpin
Student login on Anyboli platform.helpinRaunakKeshri1
 
Mastering the Unannounced Regulatory Inspection
Mastering the Unannounced Regulatory InspectionMastering the Unannounced Regulatory Inspection
Mastering the Unannounced Regulatory InspectionSafetyChain Software
 
Z Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot GraphZ Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot GraphThiyagu K
 
Industrial Policy - 1948, 1956, 1973, 1977, 1980, 1991
Industrial Policy - 1948, 1956, 1973, 1977, 1980, 1991Industrial Policy - 1948, 1956, 1973, 1977, 1980, 1991
Industrial Policy - 1948, 1956, 1973, 1977, 1980, 1991RKavithamani
 
Nutritional Needs Presentation - HLTH 104
Nutritional Needs Presentation - HLTH 104Nutritional Needs Presentation - HLTH 104
Nutritional Needs Presentation - HLTH 104misteraugie
 
Introduction to AI in Higher Education_draft.pptx
Introduction to AI in Higher Education_draft.pptxIntroduction to AI in Higher Education_draft.pptx
Introduction to AI in Higher Education_draft.pptxpboyjonauth
 
Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Celine George
 
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...EduSkills OECD
 
Organic Name Reactions for the students and aspirants of Chemistry12th.pptx
Organic Name Reactions  for the students and aspirants of Chemistry12th.pptxOrganic Name Reactions  for the students and aspirants of Chemistry12th.pptx
Organic Name Reactions for the students and aspirants of Chemistry12th.pptxVS Mahajan Coaching Centre
 
18-04-UA_REPORT_MEDIALITERAСY_INDEX-DM_23-1-final-eng.pdf
18-04-UA_REPORT_MEDIALITERAСY_INDEX-DM_23-1-final-eng.pdf18-04-UA_REPORT_MEDIALITERAСY_INDEX-DM_23-1-final-eng.pdf
18-04-UA_REPORT_MEDIALITERAСY_INDEX-DM_23-1-final-eng.pdfssuser54595a
 
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Sapana Sha
 
microwave assisted reaction. General introduction
microwave assisted reaction. General introductionmicrowave assisted reaction. General introduction
microwave assisted reaction. General introductionMaksud Ahmed
 
Grant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingGrant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingTechSoup
 
Introduction to ArtificiaI Intelligence in Higher Education
Introduction to ArtificiaI Intelligence in Higher EducationIntroduction to ArtificiaI Intelligence in Higher Education
Introduction to ArtificiaI Intelligence in Higher Educationpboyjonauth
 
How to Make a Pirate ship Primary Education.pptx
How to Make a Pirate ship Primary Education.pptxHow to Make a Pirate ship Primary Education.pptx
How to Make a Pirate ship Primary Education.pptxmanuelaromero2013
 
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptx
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptxPOINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptx
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptxSayali Powar
 
Accessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactAccessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactdawncurless
 

Dernier (20)

Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)
 
Student login on Anyboli platform.helpin
Student login on Anyboli platform.helpinStudent login on Anyboli platform.helpin
Student login on Anyboli platform.helpin
 
Mastering the Unannounced Regulatory Inspection
Mastering the Unannounced Regulatory InspectionMastering the Unannounced Regulatory Inspection
Mastering the Unannounced Regulatory Inspection
 
TataKelola dan KamSiber Kecerdasan Buatan v022.pdf
TataKelola dan KamSiber Kecerdasan Buatan v022.pdfTataKelola dan KamSiber Kecerdasan Buatan v022.pdf
TataKelola dan KamSiber Kecerdasan Buatan v022.pdf
 
Z Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot GraphZ Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot Graph
 
Industrial Policy - 1948, 1956, 1973, 1977, 1980, 1991
Industrial Policy - 1948, 1956, 1973, 1977, 1980, 1991Industrial Policy - 1948, 1956, 1973, 1977, 1980, 1991
Industrial Policy - 1948, 1956, 1973, 1977, 1980, 1991
 
Nutritional Needs Presentation - HLTH 104
Nutritional Needs Presentation - HLTH 104Nutritional Needs Presentation - HLTH 104
Nutritional Needs Presentation - HLTH 104
 
Introduction to AI in Higher Education_draft.pptx
Introduction to AI in Higher Education_draft.pptxIntroduction to AI in Higher Education_draft.pptx
Introduction to AI in Higher Education_draft.pptx
 
Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17
 
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...
 
Organic Name Reactions for the students and aspirants of Chemistry12th.pptx
Organic Name Reactions  for the students and aspirants of Chemistry12th.pptxOrganic Name Reactions  for the students and aspirants of Chemistry12th.pptx
Organic Name Reactions for the students and aspirants of Chemistry12th.pptx
 
18-04-UA_REPORT_MEDIALITERAСY_INDEX-DM_23-1-final-eng.pdf
18-04-UA_REPORT_MEDIALITERAСY_INDEX-DM_23-1-final-eng.pdf18-04-UA_REPORT_MEDIALITERAСY_INDEX-DM_23-1-final-eng.pdf
18-04-UA_REPORT_MEDIALITERAСY_INDEX-DM_23-1-final-eng.pdf
 
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
 
microwave assisted reaction. General introduction
microwave assisted reaction. General introductionmicrowave assisted reaction. General introduction
microwave assisted reaction. General introduction
 
Grant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingGrant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy Consulting
 
Introduction to ArtificiaI Intelligence in Higher Education
Introduction to ArtificiaI Intelligence in Higher EducationIntroduction to ArtificiaI Intelligence in Higher Education
Introduction to ArtificiaI Intelligence in Higher Education
 
How to Make a Pirate ship Primary Education.pptx
How to Make a Pirate ship Primary Education.pptxHow to Make a Pirate ship Primary Education.pptx
How to Make a Pirate ship Primary Education.pptx
 
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptx
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptxPOINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptx
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptx
 
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptxINDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
 
Accessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactAccessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impact
 

Flip flop& RAM ROM

  • 1. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 Lecture 8: Sequential Logic Latches & Flip-flops  Introduction  Memory Elements  Pulse-Triggered Latch S-R Latch  Edge-Triggered Flip-flops S-R Flip-flop D Flip-flop J-K Flip-flop T Flip-flop CS1104-11 1
  • 2. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 Introduction  A sequential circuit consists of a feedback path, and employs some memory elements. CS1104-11 Introduction 2 Combinational logic Memory elements Combinational outputs Memory outputs External inputs Sequential circuit = Combinational logic + Memory Elements
  • 3. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 Introduction  There are two types of sequential circuits:  synchronous: outputs change only at specific time  asynchronous: outputs change at any time Multivibrator: a class of sequential circuits. They can be:  bistable (2 stable states)  monostable or one-shot (1 stable state)  astable (no stable state)  Bistable logic devices: latches and flip-flops.  Latches and flip-flops differ in the method used for changing their state. CS1104-11 Introduction 3
  • 4. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 Memory Elements  Memory element with clock. Flip-flops are memory elements that change state on clock signals.  Clock is usually a square wave. CS1104-11 Memory Elements 4 command Memory element stored value Q clock Positive edges Negative edges Positive pulses
  • 5. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 Memory Elements  Two types of triggering/activation:  pulse-triggered  edge-triggered  Pulse-triggered  latches  ON = 1, OFF = 0  Edge-triggered  flip-flops  positive edge-triggered (ON = from 0 to 1; OFF = other time)  negative edge-triggered (ON = from 1 to 0; OFF = other time)CS1104-11 Memory Elements 5
  • 6. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 S-R Latch Complementary outputs: Q and Q'.  When Q is HIGH, the latch is in SET state.  When Q is LOW, the latch is in RESET state.  For active-HIGH input S-R latch (also known as NOR gate latch), R=HIGH (and S=LOW) a RESET state S=HIGH (and R=LOW) a SET state both inputs LOW a no change both inputs HIGH a Q and Q' both LOW (invalid)! CS1104-11 S-R Latch 6
  • 7. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 S-R Latch  For active-LOW input S'-R' latch (also known as NAND gate latch), R'=LOW (and S'=HIGH) a RESET state S'=LOW (and R'=HIGH) a SET state both inputs HIGH a no change both inputs LOW a Q and Q' both HIGH (invalid)!  Drawback of S-R latch: invalid condition exists and must be avoided. CS1104-11 S-R Latch 7
  • 8. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 S-R Latch  Characteristics table for active-high input S-R latch:  Characteristics table for active-low input S'- R' latch: CS1104-11 S-R Latch 8 S R Q Q' 0 0 NC NC No change. Latch remained in present state. 1 0 1 0 Latch SET. 0 1 0 1 Latch RESET. 1 1 0 0 Invalid condition. S' R' Q Q' 1 1 NC NC No change. Latch remained in present state. 0 1 1 0 Latch SET. 1 0 0 1 Latch RESET. 0 0 1 1 Invalid condition. S R Q Q' S R Q Q'
  • 9. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 S-R Latch  Active-HIGH input S-R latch  Active-LOW input S’-R’ latch CS1104-11 S-R Latch 9 R S Q Q' S R Q Q' 1 0 1 0 initial 0 0 1 0 (afer S=1, R=0) 0 1 0 1 0 0 0 1 (after S=0, R=1) 1 1 0 0 invalid! S' R' Q Q' 1 0 0 1 initial 1 1 0 1 (afer S'=1, R'=0) 0 1 1 0 1 1 1 0 (after S'=0, R'=1) 0 0 1 1 invalid! S' R' Q Q' S' R' Q Q' 0 1 1 0 0 0 1 0 1 0 0 1 0 0 0 1 1 1 0 0
  • 10. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 J-K Flip-flop  J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.  No invalid state.  Include a toggle state. J=HIGH (and K=LOW) a SET state K=HIGH (and J=LOW) a RESET state both inputs LOW a no change both inputs HIGH a toggle CS1104-11 J-K Flip-Ffop 10
  • 11. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 J-K Flip-flop J-K flip-flop.  Characteristic table. CS1104-11 J-K Flip-flop 11 J Q Q' CLK Pulse transition detector K J K CLK Q(t+1) Comments 0 0  Q(t) No change 0 1  0 Reset 1 0  1 Set 1 1  Q(t)' Toggle Q J K Q(t+1) 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 Q(t+1) = J.Q' + K'.Q
  • 12. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3Memory Main memory consists of a number of storage locations, each of which is identified by a unique address The ability of the CPU to identify each location is known as its addressability Each location stores a word i.e. the number of bits that can be processed by the CPU in a single operation. Word length may be typically 16, 24, 32 or as many as 64 bits. A large word length improves system performance, though may be less efficient on occasions when the full word length is not used
  • 13. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 Calculating the Maximum Capacity of Memory in a Computer • Max capacity = • number of address x capacity of each location Example What is the maximum amount of memory in a system which has a 16 bit data bus and a 24 bit address bus? Answer 224 x 2 16777216 x 2 33554432 bytes 32768 Kb 32Mb
  • 14. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3Types of main memory There are two types of main memory, Random Access Memory (RAM) and Read Only Memory (ROM) Random Access Memory (RAM) holds its data as long as the computer is switched on All data in RAM is lost when the computer is switched off Described as being volatile It is direct access as it can be both written to or read from in any order Its purpose is to temporarily hold programs and data for processing. In modern computers it also holds the operating system
  • 15. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 Types of RAM 1. Dynamic Random Access Memory (DRAM) • Contents are constantly refreshed 1000 times per second • Access time 60 – 70 nanoseconds Note: a nanosecond is one billionth of a second! 2. Synchronous Dynamic Random Access Memory (SDRAM) • Quicker than DRAM • Access time less than 60 nanoseconds 3. Direct Rambus Dynamic Random Access Memory (DRDRAM) • New type of RAM architecture • Access time 20 times faster than DRAM • More expensive
  • 16. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 4. Static Random Access Memory (SRAM) • Doesn’t need refreshing • Retains contents as long as power applied to the chip • Access time around 10 nanoseconds • Used for cache memory • Also for date and time settings as powered by small battery 5. Cache memory • Small amount of memory typically 256 or 512 kilobytes • Temporary store for often used instructions • Level 1 cache is built within the CPU (internal) • Level 2 cache may be on chip or nearby (external) • Faster for CPU to access than main memory Types of RAM
  • 17. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 The operation of cache memory 1. Cache fetches data from next to current addresses in main memory 2. CPU checks to see whether the next instruction it requires is in cache 3. If it is, then the instruction is fetched from the cache – a very fast position 4. If not, the CPU has to fetch next instruction from main memory - a much slower process Main Memory (DRAM) CPU Cache Memory (SRAM) = Bus connections
  • 18. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3Types of RAM 6. Virtual memory • Uses backing storage e.g. hard disk as a temporary location for programs and data where insufficient RAM available • Swaps programs and data between the hard-disk and RAM as the CPU requires them for processing • A cheap method of running large or many programs on a computer system • Cost is speed: the CPU can access RAM in nanoseconds but hard-disk in milliseconds (Note: a millisecond is a thousandth of a second) • Virtual memory is much slower than RAM
  • 19. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3Read only memory (ROM) ROM holds programs and data permanently even when computer is switched off Data can be read by the CPU in any order so ROM is also direct access The contents of ROM are fixed at the time of manufacture Stores a program called the bootstrap loader that helps start up the computer Access time of between 10 and 50 nanoseconds
  • 20. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 Types of ROM 1. Programmable Read Only Memory (PROM) • Empty of data when manufactured • May be permanently programmed by the user 2. Erasable Programmable Read Only Memory (EPROM) • Can be programmed, erased and reprogrammed • The EPROM chip has a small window on top allowing it to be erased by shining ultra-violet light on it • After reprogramming the window is covered to prevent new contents being erased • Access time is around 45 – 90 nanoseconds
  • 21. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3Types of ROM 3. Electrically Erasable Programmable Read Only Memory (EEPROM) • Reprogrammed electrically without using ultraviolet light • Must be removed from the computer and placed in a special machine to do this • Access times between 45 and 200 nanoseconds 4. Flash ROM • Similar to EEPROM • However, can be reprogrammed while still in the computer • Easier to upgrade programs stored in Flash ROM • Used to store programs in devices e.g. modems • Access time is around 45 – 90 nanoseconds 5. ROM cartridges • Commonly used in games machines • Prevents software from being easily copied
  • 22. Subject Name Code Credit Hours Digital Electronics and Logic Design DEL-244 3 End of segment