ChipStart is a global semiconductor intellectual property (IP) solutions company headquartered in Palo Alto, California. ChipStart provides sales, marketing, and support engagement solutions for companies that commerce third party semiconductor intellectual property. ChipStart is also a developer of high-quality, highly-differentiated, pre-verified IP subsystem solutions, macros, analog/mixed-signal (AMS) foundry services, and related design services for ASIC and fabless semiconductor companies.
2. TM
Mission Statement
ž To be the leading supplier of integrated,
next-generation semiconductor intellectual
property System-on-Chip subsystems and
silicon solutions, accelerating the
implementation and realization of our
customers products
18 July 2014 ChipStart LLC - CONFIDENTIAL
We Differentiate Your
Core Competence
3. TM
Chipstart Management
ChipStart LLC - CONFIDENTIAL
Director Position Background
Howard Pakosh President & CEO Virage Logic, Magma Design Automation, Synopsys and TEAM
Corporation
Former co-founder of Xentec, a startup focusing on
semiconductor IP sold to InSilicon (December 2000), then
acquired by Synopsys (March 2002)
Mark De Souza Executive VP & COO Virage Logic, Ikos Systems, ST Microelectronics and De Beers
Former co-founder of Atinec, a VC-funded EDA Startup
focusing on simulation acceleration
Chris Keil VP Business Development RMI, Virage Logic, Novocell Semiconductor, LSI Logic and
TEAM Corporation
Jim Fleury Director, Architectural BU Intel, MIPS, ARC, Sonics, VAST Systems and Tensilica
4. TM
ChipStart
Global
Northeast/Canada
Boston, Toronto,
Ottawa
Silicon Valley
San Jose
Santa Clara
Northwest
Portland, Vancouver
Central
Austin, Dallas,
Colorado Springs
Israel
Haifa, Tel Aviv
North
UK , Scandinavia
South
France , Italy, BeNeLux
Central
Germany, Austria
4
ChipStart Offices
Key Customer Centers
China
Key centers: Beijing,
Shanghai, Shenzhen
Taiwan
Key centers:
Hsinshu
Japan
Key centers: Tokyo,
Yokohama
Korea
Key centers: Seoul
North America
Europe
Asia
SSM R&D Center
Irvine, CA
Memory R&D
Center
Kiev
5. TM
ChipStart
Strategic Solution Initiatives
ž Objectives
— Offer “Best-in-Class” solutions to its customers
— Differentiated from other manufacturers reps
because ChipStart is adding value to each
customer engagement
18 July 2014 ChipStart LLC - CONFIDENTIAL
7. TM
Architecture Tape OutRTL Design
Physical
Layout
Architectural IP
§ System-level management
§ Processors
§ Register management
§ Bus fabric selection
Typical Design Cycle
ChipStart LLC - CONFIDENTIAL
Verification
Finalize Foundry Selection
Digital / Security IP
§ RTL macros
§ Digital audio and/or video subsystems
§ Protocol selection
§ Various controllers
§ Memory scheduling and arbitration
Foundation or Physical IP
§ Standard cells, embedded memories
and various I/O
§ High-speed I/O
§ PLL/DLL
§ PHYs or SERDES
§ Various analog/mixed-signal macros
Wherever IP is selected at various
points in the design cycle…
ChipStart is there!
As an IP Developer, ChipStart
enters the sales cycle here.
As an IP Integrator, ChipStart
enters the sales cycle here.
As an IP Aggregator, ChipStart can
enter the sales cycle anywhere.
8. TM
ChipStart IP Portfolio
DDR or
HMC
PHY
PLL
Digital
IP
Foundation
IP
Architectural IPInterface
IP
ADC
DAC
AFE
DDR Memory
Scheduler
FEC/
LDPC
SoC
System
Manager
AXI/AHBBusFabric/Interconnect
H.264
HEVC
VP9
SRAM
OTP
TCAM/
BCAM
Low Power
SRAM
HDMI/
HDP HDMI PHY
PCI
MIPI
MIPI
PHY
SATA
USB
Multiprotocol
PHY
DDR or
HMC
Re-Configurable
or Hardened
Processors
Embedded
FPGA
Security IP
10. TM
Integrated Subsystem Solutions
Controller & PHY VIP
HMC Late Q3/14
DDR 2/3/4 Available
PCI II/III Semi-Integrated
MIPI Semi-Integrated
SATA II/III
Semi-Integrated
USB II/III Available
11. TM
Subsystem Solution Map
Controller PHY Verification
HMC
a. TekStart
b. Northwest Logic
a. Avago
b. OmniPHY
Pico
DDR 2/3/4
a. Uniquify
b. Northwest Logic
a. Uniquify
b. Dolphin
c. SilabTech
Avery Design
PCI II/III Northwest Logic
a. Mixel
b. SilabTech
Avery Design
MIPI Northwest Logic
a. Mixel
b. SilabTech
SmartDV
SATA II/III
a. ASICS WS
b. Faraday
a. SilabTech
b. Terminus Circuits
SmartDV
USB II/III
a. ASICS WS
b. Faraday
a. Faraday (UMC)
b. SilabTech
c. Terminus Circuits
Avery Design
13. TM
ChipStart Strategic Solution Partners
ChipStart LLC - CONFIDENTIAL
SANKALP
s e m i c o n d u c t o r
avery
design systems
Berkeley Analog
ocean logic!
14. TM
14
Single License Agreement
ChipStart LLC CONFIDENTIAL
ž Selling IP on technical merit only ½ the job
ž License negotiation is PAINFUL for both buyer and seller
— Warranty
— Indemnification
— Liabilities
ž Insurance Broker Comparison
— Do you buy car, home, life and medical insurance from 4 different underwriters?
— Most choose to work with a broker
○ Broker’s value: Combining policies to create a lower price in a fraction of the time
it would take to negotiate all separately
ž By combining multiple IP’s on one agreement Chipstart offers:
— Multi-product discount
— Majority of ChipStart vendor partners participate
— License Agreement underwritten by industry-leading insurance underwriter
— Customer allowed to mitigate risk by adding higher liability amounts
Our Number 1 Value-Add!
15. TM
IP Cores and Embedded Software
18 July 2014 ChipStart LLC - CONFIDENTIAL
20. TM
2014 - HMC Key Features
ž HMC Spec Compliant
— Full-width Link and Half-width Link support
— 10, 12.5, 15 Gbit/s lane support
ž ASIC & FPGA support
— Delivered integrated with target PHY
ž 1024 and 512 bit Core Width options
— Enables clock frequency to be tailored to target technology,
easing timing closure
ž MultiPort AXI-4 Interface option
— AXI-4 widths: 1024, 512, 256, 128, 64 bits
— Up to 32 ports
— AXI-3 Support provided with wrapper file
ChipStart LLC - CONFIDENTIAL
21. TM
2014 - HMC Spec Compliance
ž All HMC Controller Abstraction
Layers
— Transaction Layer
— Link Layer
— Logical Sub-block of Physical layer
ž Link initialization and training
ž Retries
ž CRC generation and checking
ž Link management and monitoring
ž Link layer flow control
ž Support for HMC device chaining
ž Low power mode support
ž Atomic command support
ž Bit write commands
ChipStart LLC - CONFIDENTIAL
Target
Clock
Frequencies
(ASIC)
Link
Lane
Rate
(GB/
s)
Core
Width
(Bits)
Core
Freq
(MHz)
Full
15
1024
234
Full
10
1024
156
Full
15
512
469
Full
10
512
313
Half
15
512
234
Half
10
512
156
22. TM
2014 - HMC PHY Support
ž Third-party PHYs supporting HMC
— Avago (30GB/s), available today
— OmniPHY (30GB/s), available Q1/2015
ž HMCC is fully integrated and validated with the
specified PHY
— Licensing options available upon request
ž Support & Maintenance
— TekStart provides full support for the controller or the
integrated controller/PHY solution
— PHY vendor collaboration ensures all customer questions
are addressed
ChipStart LLC - CONFIDENTIAL
23. TM
www.Performance-IP.com – Company Confidential
– NDA Required
2014 - Memory Request Optimizer
● Reduces Latency
● Reduces Bandwidth
● Works with multiple clients
● Widely divergent requests
● Programmable Optimization
● None, Low, Moderate, & Aggressive
● Dramatic reduction in read latency across
all applications and all MRO modes
● Resulted in an increase in CPU IPC
MRO
Optimization
% of IPC Improvement
App1 App2
MP3
Decode
Mode 1 11.1 14.0 8.8
Mode 2 13.0 14.0 14.1
Mode 3 14.4 15.5 15.7
24. TM
2014 - L2+ Cache
ž Features:
— Configurable Level2 Cache
○ Cache Size
○ Number of Ways
○ Cache Line Size
— Memory Tracker TechnologyTM
— Control Registers accessed via
Processor I/F
— Fully synchronous design, push
button synthesis and static timing
analysis
— Written in Verilog-2001
18 July 2014 ChipStart LLC - CONFIDENTIAL
25. TM
2014 - DMA Controller
ž Features:
— 8 Independent DMA Channels
○ Support AXI4 Protocol
○ Configurable AXI Bus Width
○ 32b, 64b, or 128b widths supported
○ Supported DMA Transfers
○ Memory to Memory
○ Memory to Peripheral
○ Peripheral to Memory
○ Peripheral to Peripheral
— Processor Interrupt Support
— Channel arbiter with two level round-robin arbitration
— Integrated RAM Buffer
— Control Registers accessed via AXI4-Lite I/F
— Fully synchronous design, push button synthesis and static timing
analysis
— Written in Verilog-2001
18 July 2014 ChipStart LLC - CONFIDENTIAL
26. TM
2014 – Low Leakage Memories
ž 70% Lower Power
— Includes both active (switching) & standby (leakage)
— Bit cell is optimized for leakage in a given area target
ž Enables Single-Rail Design
— Vmin= Vlogic_min
— No process cheats
○ Logic rules design
○ No waivers
○ Standard logic process
— No additional DC-DC converters
ž Robust Bit Cell
— Only 2 compilers required (Single-Port, Dual-Port)
○ SP + DP = SP + DP + 1PRF + 2PRF + 2P
ž Faster Performance Than Foundry HS Bit Cell
ž Area Efficient
ž Improved Yield
— Variation tolerant, highly manufacturable
18 July 2014 ChipStart LLC - CONFIDENTIAL
27. TM
2014 - Hardware/Software
Development Platform
ž Allows true multicore design
ž Any number of CPU’s from any number of
CPU vendors
18 July 2014 ChipStart LLC - CONFIDENTIAL
Single or Multiple
Processors
+ Modeled environment+ peripherals (RTL or Model)
Subsystem
28. TM
2014 - Hardware/Software
Development Platform
ž Features
— Unified SW/HW co-verification in single environment
— Fast cycle-accurate Instruction Set Simulators
— Simultaneous multi-core simulations in single environment
— Combining processors of different manufacturers
— Ultra Fast Verilog & VHDL RTL simulation
— Cycle-based RTL simulators
— Static & Dynamic profiler and HDL design navigator
— Start SW/HW co-verification without hardware target
ž Benefits
— Reduction of development time by 30%
— Increasing “First time right” chance by 80%
— Software & hardware engineers use the same tool
— Mutual development and use of SW/HW test benches
— New (and customer specific) processor types fit in the same tool
— Splendid return on investment
18 July 2014 ChipStart LLC - CONFIDENTIAL
30. TM
2014 – SerDes/PHY IP Solutions
18 July 2014 ChipStart LLC - CONFIDENTIAL
Segment Standard Data Rate (Gbps)
PCIe
– Graphics, embedded IO’s
• PCI Express Gen 2
• PCI Express Gen 3
• 5 Gbps
• 8 Gbps
CEI
– LR, SR
• CEI 6.4G LR/SR • 6.25Gbps
XFI / SFI • Optical communications
• XFI: Specifications at the interface
between SERDES and XFP module
(electro-optical module)
• SFI: Specifications at the interface
between SERDES and SFF module
(electro-optical module)
• 9.95Gbps to 10.55Gbps
Fibre Channel
– Storage Area Network
• 4GFC
• 8GFC
• 4.25 Gbps
• 8.5 Gbps
Ethernet
– Local and Wide Area Network
• XAUI
• KR4: backplane applications
• 10G Ethernet
• KR: backplane applications
• CR: copper cable interconnect
• 4x 3.125Gbps . 10GBase-X
• 10.3125Gbps . 10GBase-R
SATA • SATA G2/G3 • 3 Gbps
• 6 Gbps
SAS • SAS 6.0G
• SAS 3.0G
• 6 Gbps
• 3 Gbps
31. TM
2014 – SerDes/PHY IP Solutions
ž High-Speed I/O
— 2.5GB / 5GB serdes/PHY
— 6GB / 10GB / 12.5GBPS Multi-protocol serdes/PHY
— Multi-foundry support
18 July 2014 ChipStart LLC - CONFIDENTIAL
TRANSMITTER
C
O
N
C
O
N
20dB loss 2-connector
TX
PKG
RECEIVER
f
C
P /2
/N
FREF
FREQ
PLL
RX
PKG
FF
E
8:
2 DRV
CL
K
VGA
/
PKA
MP
DFE5
2:8 De-
Ser
CDRPI
32. TM
2014 – Embedded Sensors
ž Embedded Temperature Die Sensor
— Temperature sensing an issue due to
○ Transistor leakage at low geometries
○ High gate densities
○ High clock frequencies
○ Wide process variations across wafer
— Uses
○ Performance optimization
○ Thermal management
○ Silicon characterization and management
○ Failure management
— Foundry Support
○ TSMC
— 65LP, 40LP, 40G, 28HP and 28HPM
— 20nm SOI (coming soon)
○ Global Foundries
— GF28SLP
18 July 2014 ChipStart LLC - CONFIDENTIAL
33. TM
2014 – Embedded FPGA
ž Why Use eFPGA?
— Embed programmable functions targeting
functions of limited complexity
— Prototyping
— ECO’s or metal/mask fixes
ž Benefits
— Reduce costs
— Reduce system chip count/board area
— Reduce power consumption
— Increase performance
— Maintain cost effective Field
Programmability in production volumes
18 July 2014 ChipStart LLC - CONFIDENTIAL
Equivalent and
re-programmable
RTL block
Prog.
block
bitstream
+
Soft IP
re-useSoft IP re-use
Soft IP re-use
New HDL block
Hard
IP
Hard IP Hard IP
ASIC
Prog.
block
Prog.
block
34. TM
2014 – PLL Solutions
ž High-Speed Digital PLL
— Silicon proven (TSMC 65nm and 40nm)
— Totally-integrated clock-driver and clock-multiplying-unit IP block
○ No off-chip components
○ Fractional-N division included for non-integer clock multiplication and
spreading
○ Intended for applications such as:
— CMU in a SERDES block at data rates as high as +15 GBPS
— Clock-driver applications where the frequencies are not integrally related
— Specs
○ Frequency: 200MHz and 7.5GHz over process corners
○ Temperature: -40 to 125 degrees C
○ Power: 32mW (@ 5GHz output)
○ Jitter: 1.0pS (accumulated) @ 5GHz
○ Area: 0.11 mm^2
18 July 2014 ChipStart LLC - CONFIDENTIAL
35. TM
2014 – DDR Subsystem Solutions
ž Integrated DDR
Controller & PHY
— DDR Controller
○ Includes Patented Self-
Calibrating Logic (SCL)
○ Guarantees the best possible
system-level timing margin
○ Ease of timing closure at high
speed
○ Configures all system level
timing parameters on the fly
— SCL logic configures all necessary timing
parameters every time system is reset
○ Increases chip/system yield at
production
18 July 2014 ChipStart LLC - CONFIDENTIAL
SSTL/HSTL
I/O
SCL/DSCL
36. TM
2014 – DDR Subsystem Solutions
— DDR PHY
○ Ultra low power design
○ Eliminates tough DDR timing
issues such as data skew, clock
skew, and setup/hold time
○ Highly automated porting process
— Port time to new process nodes is 4-6
weeks
○ Reduces risk by eliminating
variability across different byte-
lanes
○ Highly configurable/flexible
— Compiler is tuned for Industry standard
library set
— Supports rectilinear shapes
○ Supports industry standard 3rd
party DDR SSTL I/O’s
18 July 2014 ChipStart LLC - CONFIDENTIAL
Tech Process (nm)
Speed
(MHz)
DRAM
type
DRAM Vendor Status
GF 65 G 400 DDR2 Micron Silicon Proven
GF 65 G 800 DDR3 Tapeout in Oct 2011
GF 65 G 600 DDR3 Tapeout Q3 2012
GF 65 G (Emerald) 400 DDR2 Silicon Proven
GF 65G ? LPDDR2
SMIC 533 DDR3 Tapeout Date TBD
SMIC 90 G 400 DDR2 Silicon Proven
TSMC 28HPM 1066 DDR3
Test chip tapeout June
2012
TSMC 28HPM 666 DDR3 Tapeout Q1 2014
TSMC 40 G 900 DDR3 Tapeout in Q4 2012
TSMC 40 G
666 DDR3 Hynix Tapeout in May 2012
2.5V IO oxide
TSMC 40 LP 800 DDR3 Hynix Silicon Proven
TSMC 40G 1.8V IO
oxide
1066 DDR3 Tapeout June 2012
TSMC 40LP 933 DDR3
TSMC 40LP 800 DDR3 Tapeout Q3 2012
TSMC 65 G 533 DDR3 Silicon Proven
TSMC 65G 340 DDR3 Tapeout Date TBD
TSMC 65G 800 DDR3 Silicon Q3 2012
TSMC 65G 800 DDR3
TSMC 65G 800 DDR3
TSMC 65nm LP 166 LPDDR Silicon Proven
TSMC 90 G 800 DDR3
Micron /
Samsung
Silicon Proven
TSMC 90 G (Topaz) 400 DDR2 Etron / Winbond Silicon Proven
TSMC 90LP 333 DDR2 Tapeout Date TBD
UMC 90 LP 166 LPDDR Micron Silicon Proven
37. TM
2014 – Custom Memory Design
ž SRAM Memories
— Great demand for low leakage memories or
memories that operate at lower voltages
— Optimized for standby power
○ Uses standard Vt and high Vt MOSFETs
— Deep sleep mode shuts down the power to
all peripheral circuitry and to selected banks
of SRAM cells
— Conventional row-column physical decoding
— Segmented bitline architecture used to
improve speed and reduce active power
consumption
— Foundry Support:
○ TSMC 0.18um down to 28nm HPM
○ GF 0.25um down to 28nm
○ Others available upon request
18 July 2014 ChipStart LLC - CONFIDENTIAL
38. TM
2014 – CAM’s
18 July 2014 ChipStart LLC - CONFIDENTIAL
ž Industry-leading compilable CAM at advanced process
nodes
— Allows customers to generate ANY size CAM
○ 40Mb monolithic TCAM done for a large networking chip
○ Near-custom CAM at minimal implementation cost
○ Various options
— Multi-bank,
pipeline and
integrated 2-
cycle CAM-RAM
(lookup)
○ Multiple
architectural
trade-offs to
achieve required
PPA
39. TM
2014 – Turnkey Design by Delta
ž Design services
§ Interface at any level from specification to GDSII
§ Experienced team (in-house and partners)
§ Flexible business model
§ IP sourcing and integration
ž Manufacturing
§ Prototype and high volume test in-house
§ Wafer procurement and production at leading
foundries
§ Package engineering and production at top
assembly houses
§ Failure analysis and qualification
§ Logistics and supply chain management all from
one source
18 July 2014 ChipStart LLC - CONFIDENTIAL
ž Complete Turnkey Services
— Total ASIC solutions
— Design and development
— Packaging solutions
— Production & component supply
— Test development & production testing
— Component qualification
— Materials & component technology
— Complete Sensor solutions
40. TM
IP Cores and Embedded Software
18 July 2014 ChipStart LLC - CONFIDENTIAL
42. TM
Today’s Performance SoCs Require
Complex System Management
Samsung Apps Processor (iPhone3) OMAP 4
4+ Compute Engines 4-5 Memory Interfaces
More than 1000 Applications
How Do You Guarantee Proper
Hardware State Changes for +1000 Applications?
43. TM
System Management Complexity
Rises Exponentially with Logic Growth
Source: Advance Tech Marketing
SystemManagement
Complexity
High
Low
Basic
SoC Type
Value Performance
SSM Adoption Range
Based on Complexity
(circa 2011)
44. TM
System Management Complexity
Has Past a Key Threshold
IP Block (functional test)
Interconnect/Dataflow
(Performance Testing)
Single Application
Sequencing
(Simple H/W State Changes)
Multiple Application
Sequencing
(Complex (aka random)
H/W state changes)
1995
2000
2005
2010
System Operation Verification Complexity
(Logarithmic)
Limited System Management for Multi-
sequencing Means Complex System
Operation Verification and
High Risk Cost/TTM Tradeoffs
When Using Traditional Methods
10X 100X 1000X
Source: Advance Tech Marketing
SoC System Operation
Verification Tasks
45. TM
High Risk Cost/TTM Tradeoffs Now Driven
By Inadequate SoC Architecture
ž TradiConal
(Host
CPU
acts
as
System
Manager)
ž Interconnect
Based
(Adding
Control
to
Data
Flows)
These Approaches Were Not Designed to Manage
1000+ Applications Using the Same Device
Host
CPU
IP
Core
IP
Core
I/O
IP
Core
IP
Core
Host CPU no longer has adequate visibility and control
For complex Multicore SoCs
Control functions complicate global interconnect design,
experience execution delays, and degrades efficiency
Of high performance data flows
Host
CPU
IP
Core
IP
Core
I/O
46. TM
Control Plan Architectures
Reduce Complexity and Ease Tradeoffs
System
Controller
Low
Speed
I/O
Media
Engine
High
Speed
I/O
DRAM
Controller
DSPCPU
Global Interconnect
Control Plane
System
Controller
Low
Speed
I/O
Media
Engine
High
Speed
I/O
DRAM
Controller
DSPCPU
Global Interconnect
Control Plane
• Separation of control and data planes
make BOTH more efficient
• Independent controller has
adequate visibility for effective
control
• Programmable state management
delivers new levels of software/hardware
coupling and implementation flexibility
required for high numbers of applications
• Subsystem IP approach delivers new abstraction layers that
enables system management development acceleration and high
reuse
47. TM
Semico Forecasts High System
Management IP Growth
$0
$20
$40
$60
$80
$100
$120
$140
$160
$180
2010* 2011* 2012* 2013* 2014* 2015*
MDollars
$0
$100
$200
$300
$400
$500
$600
$700
$800
$900
$1,000
TotalMDollars
Multi Media System Resource Mgmt. Memory Security Computing Communications Video Total
48. TM
Transforming SoC Architecture Using
System Management Subsystem IP
ž Complexity
levels
now
dictate
that
System
Management
become
an
architecture
element
not
an
implementaCon
aKerthought
ž Control
plane
architectures
introduce
new
flexibility
that
improves
system
management
effecCveness
and
promotes
high
reuse
ž Subsystem
IP
approach
introduces
the
abstracCon
layers
needed
to
cost
effecCvely
manage
the
system
operaCon
complexity
explosion
Make vs. Buy Rapidly Favoring Outsourcing
49. TM
49
SSM Advantages
ž Simplifies accessibility and control of all managed IP
blocks
ž Guaranteed synchronization between hardware and
software while executing complex sequences
ž Virtualization of system management functions
— Compartmentalizes instantiation dependencies
— Improves software’s ability to control hardware
Saves Time and Money
Offers SoC Architecture Consistency
51. TM
51
SSM Addresses Key System Issues
ž Standardizes Management of Key System Functions
— Power, security, error recovery, boot sequencing
ž Eases Hardware Software Integration
ž Provides A Reusable Architecture Across Many SoCs
A Subsystem Suited for Universal Adoption
52. TM
ChipStart Overall Summary
ž ChipStart is the only, independent, one-stop semiconductor
IP solution alternative to ARM and Synopsys
ž Delivering value as an IP Developer
— System Level Management IP Solutions
— Low voltage/Low power Memory Compilers
— Integrated, On-Chip Voltage Regulators
ž Delivering value as an IP Integrator
— Subsystem Solutions oriented
ž Delivering value as an IP Aggregator
— Single License Agreement for IP Solutions
ž Talented team
— >350 years semiconductor IP experience
53. TM
ChipStart Contact Page
www.chip-start.com
ChipStart LLC
228 Hamilton Avenue 3rd Floor
Palo Alto, CA 94301
Toll-Free: (855) IP-MATTERS
International: +1.650.204.7883
Email: info@chip-start.com
ChipStart UK
Maidenhead, Berkshire SL6 4LZ
Office: +44 16 2856 6596
Eastern USA/Canada
Oakville, ON L6J 0A2
Office: +1.905.634.6688
Fax: +1.905.592.2048
Northwest USA
Evergreen, CO 80439
Office: +1. 303.506.1088
ChipStart France
91570 Bievres
Office: +33 6 82 65 28 08
ChipStart Japan
Suite 405, 1296-2 Suenaga, Takatsu-ku Kawasaki
Kanagawa 213-0013
Office: +81 90 3222 3085
ChipStart China - Shenzhen
15-18B, Hai Yin Chang Cheng, Nanshan District
Shenzhen, 518048 China P.R.C.
Office: +86 186 0300 6982
ChipStart Taiwan
5, No. 2, Lane 37, Jieyun Rd. Sanchong District
New Taipei City 241, Taiwan R.O.C.
Office: +886-955062842
ChipStart China - Shanghai
608R, building 6th, No.1050, WuZhing Rd.
Shanghai, 201103 China P.R.C.
Office: +86 13817105679
ChipStart Korea
1310,Daejong Bldg.143-48 Samseong-Dong
Gangnam-Gu
Seoul 139-090, South Korea
Office: +82 10 2205 3760