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Mahmoud Abdellatif
Mahmoud Abdellatif

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Session 0 http://www.bized.co.uk Introduction to the Course 1 Copyright 2006 – Biz/ed
Session 0 http://www.bized.co.uk Start Group 2011 Alaa Salah Shehata Abdel Rahman Mahmoud A.M. Abdel Latif Mohamed Salah Mahmoud Mohamed Mohamed Talaat contact us start.courses@gmail.com Facebook group start.group@groups.facebook.com 2 Copyright 2006 – Biz/ed
Session 0 http://www.bized.co.uk 0 Digital Design using VHDL Course Outlines -Introduction to VHDL -Statements in VHDL -Sequential Statements -Concurrent Statements -Data Objects -Data Operators -Data types -FSM finite state machines -Structural Description -Testbench -Introduction to FPGA -Implementation on FPGA 3 Copyright 2006 – Biz/ed
Session 0 http://www.bized.co.uk Each Session includes Illustration Examples Exercises Labs Refresh Your Assignment Time for your Questions Demo Memory Questions 4 Copyright 2006 – Biz/ed
Session 0 http://www.bized.co.uk Through our course there will be Mini Project Main Project 5 Copyright 2006 – Biz/ed
Session 0 http://www.bized.co.uk Start Group material Sessions Slides Start Group VHDL Summary VHDL Guide 6 Copyright 2006 – Biz/ed
Session 0 http://www.bized.co.uk Tools Used during course Xilinx ISE Modelsim 7 Copyright 2006 – Biz/ed
Session 0 http://www.bized.co.uk Finally, we hope you remember us through our attendance certification 8 Copyright 2006 – Biz/ed
Session 0 http://www.bized.co.uk See You Next Session 9 Copyright 2006 – Biz/ed

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Intrduction to the course

  • 1. Session 0 http://www.bized.co.uk Introduction to the Course 1 Copyright 2006 – Biz/ed
  • 2. Session 0 http://www.bized.co.uk Start Group 2011 Alaa Salah Shehata Abdel Rahman Mahmoud A.M. Abdel Latif Mohamed Salah Mahmoud Mohamed Mohamed Talaat contact us start.courses@gmail.com Facebook group start.group@groups.facebook.com 2 Copyright 2006 – Biz/ed
  • 3. Session 0 http://www.bized.co.uk 0 Digital Design using VHDL Course Outlines -Introduction to VHDL -Statements in VHDL -Sequential Statements -Concurrent Statements -Data Objects -Data Operators -Data types -FSM finite state machines -Structural Description -Testbench -Introduction to FPGA -Implementation on FPGA 3 Copyright 2006 – Biz/ed
  • 4. Session 0 http://www.bized.co.uk Each Session includes Illustration Examples Exercises Labs Refresh Your Assignment Time for your Questions Demo Memory Questions 4 Copyright 2006 – Biz/ed
  • 5. Session 0 http://www.bized.co.uk Through our course there will be Mini Project Main Project 5 Copyright 2006 – Biz/ed
  • 6. Session 0 http://www.bized.co.uk Start Group material Sessions Slides Start Group VHDL Summary VHDL Guide 6 Copyright 2006 – Biz/ed
  • 7. Session 0 http://www.bized.co.uk Tools Used during course Xilinx ISE Modelsim 7 Copyright 2006 – Biz/ed
  • 8. Session 0 http://www.bized.co.uk Finally, we hope you remember us through our attendance certification 8 Copyright 2006 – Biz/ed
  • 9. Session 0 http://www.bized.co.uk See You Next Session 9 Copyright 2006 – Biz/ed