Boost PC performance: How more available memory can improve productivity
Session six
1. http://www.bized.co.uk
Session 6
Prepared by
Alaa Salah Shehata
Mahmoud A. M. Abd El Latif
Mohamed Mohamed Tala’t
Mohamed Salah Mahmoud
Version 02 – October 2011
Copyright 2006 – Biz/ed
2. http://www.bized.co.uk
Contents -Scrambler mini project discussion
-Finite State Machine
-What is FSM?
-Moore machine
6
-Mealy machine
-FSM in VHDL
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What is FSM
Any digital system consists of two part:
Data Part
Data part
Responsible for the processing of data. The Inputs Outputs
processing is done through some blocks such as (full
adder, digital filter, decoder,…)
Controls
Control part
Describes how and when these blocks will
communicate with each other.
The control part is generally described using a finite
Control Part
state machine.
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What is FSM
S1
Finite State Machine
FSM is simply a finite number of states that
S3 S2
each state describes a certain set of control
outputs that are connected to the data part
blocks.
The transition between these states depends
mainly on the inputs of the FSM.
There are two main types of FSM:
S4
Moore FSM
Mealy FSM
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FSM in VHDL
Assigning Moore Outputs
Output
Use a combinational ‘process’ to model Output Logic Logic
Outputs are only dependant on the current state
Assigning Mealy Outputs Outputs = f(State)
Use a combinatorial ‘process’ to model Output Logic
Outputs are dependant on the current state & the input Outputs = f(Inputs, State)
Output
Logic
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Moore FSM
In a Moore finite state machine, the output of
the circuit is dependent only on the state of
the machine and not on its inputs.
Inputs Next Present
state state Outputs
Next Machine Output
State State Logic
Logic Registers
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Mealy FSM
In a Mealy finite state machine, the output is
dependent both on the machine state as well
as on the inputs to the FSM.
Inputs Next Present
state state Outputs
Next Machine Output
State State Logic
Logic Registers
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Moore FSM transition
condition 1
state 1 state 2
transition
condition 2
Mealy FSM transition condition 1 /
output 1
state 1 state 2
transition condition 2 /
output 2
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Moore FSM that Recognizes Sequence “10”
0 1
1 0
S0 / 0 S1 / 0 S2 / 1
reset
S0: No S1: “1” S2: “10”
Meaning elements observed observed
of states: of the
sequence
observed
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Mealy FSM that Recognizes Sequence “10”
0/0 1/0 1/0
S0 S1
reset 0/1
S0: No S1: “1”
Meaning elements observed
of states: of the
sequence
observed
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3-FSM in VHDL
-Finite State Machines Can Be Easily Described With Processes
-Synthesis Tools Understand FSM Description if Certain Rules Are Followed
-----State transitions should be described in a process sensitive to clock and asynchronous
reset signals only
-----Output function described using rules for combinational logic, i.e. as concurrent
statements or a process with all inputs in the sensitivity list
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FSM in VHDL
The “3 Processes, 1 Clocked + separate transitions/actions” style
1-Process modeling “Next State Logic” Next
State
Logic
2-Process modeling "Current State Registers"
State
Registers
3-Process modeling “Output Logic”
Output
Logic
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FSM in VHDL
Next-State Logic
Use a combinational ‘process’ to model next state logic
process ( current_state, <in1>, <in2>, <in3> … )
Begin
case ( Current_State ) is
when <state1> =>
Next
if ( <condition (<in1>, <in2>...)> ) then State
Next_State <= <state2>; Logic
elsif ( <condition (<in1>, <in2>...)> ) then
Next_State <= <state3>;
...
end process;
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FSM in VHDL
Current-State
Use a sequential ‘process’ to describe current state logic*
Process (clock)
Begin
if rising_edge (clock) then
if ( reset = '1' ) then -- synchronous reset
Current_State <= <reset_state>;
else
Current_State <= Next_State; State
Registers
end if;
end if;
end process;
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Vending Machine
Specifications
-Deliver package of gum after 15 piaster deposited
-Single coin slot for 5 and 10 piasters
Step 1 : Understand the problem
Draw a block diagram
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Step 2 : Draw a state diagram
Reset
D S0 N
S6 S1
D N D N N = 5 piaster
S8 S7 S3 S2 D = 10 piaster
open open open D N
S5 S4
open open
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Step 3 : State Minimization
Reset
S0
N
S1 D
N N = 5 piaster
D D = 10 piaster
S2
N,D
S3
open
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Step 4
Write VHDL code (Moore)
Inputs and Outputs Reset
S0
library IEEE; N
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
S1 D
use IEEE.STD_LOGIC_UNSIGNED.ALL;
N
entity vend_machine_moore is D
Port (N : in STD_LOGIC; S2
D : in STD_LOGIC;
reset : in STD_LOGIC; N,D
clk : in STD_LOGIC; S3
tank_open : out STD_LOGIC);
end vend_machine_moore;
open
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Define the states Reset
We need to define a new type for the names of the states
S0
N
S1 D
architecture Behavioral of vend_machine_moore is
N
type states is (s0,s1,s2,s3); D S2
signal n_state,p_state :states;
begin N,D
S3
open
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The transition process Reset
Responsible for the transition of states from present state to next state.
S0
N
transition :process(clk,reset) S1 D
begin
if reset='1' then N
p_state <=s0 ; D
elsif rising_edge(clk) then S2
p_state <= n_state ;
end if; N,D
end process transition; S3
open
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Next State logic process
Responsible for generating the next state logic.
Reset
next_state :process(N,D,p_state)
--p_state in list to trigger process if ips are constants S0
begin
case p_state is N
when s0 => when s2 =>
if N='1' then if N='1' then S1 D
n_state <= s1; n_state <= s3;
elsif D='1' then elsif D='1' then
n_state <= s2; n_state <= s3;
N
else
n_state <= s0;
else n_state <= s2; D S2
end if;
end if;
when s1 => when s3 => N,D
if N='1' then n_state <= s0;
n_state <= s2; -------------- S3
elsif D='1' then end case;
n_state <= s3;
else n_state <= s1;
end process next_state; open
end if;
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Output logic process
Responsible for generating the output logic. Reset
output_logic :process(p_state)
S0
begin
case p_state is N
when s0 => tank_open <='0'; S1
when s1 => tank_open <='0';
D
when s2 => tank_open <='0';
when s3 => tank_open <='1'; N
end case; D S2
end process output_logic ;
N,D
end Behavioral; S3
open
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Step 4
Write VHDL code (Mealy)
Reset
Note : the number of states in Mealy FSM 3 !!
library IEEE; S0
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; N, 0
entity vend_machine_moore is N/D, 1 D, 1 S1 D, 0
Port (N : in STD_LOGIC;
D : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
N, 0
tank_open : out STD_LOGIC);
end vend_machine_moore; S2
architecture Behavioral of vend_machine_mealy is
type states is (s0,s1,s2);
signal n_state,p_state :states;
begin
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transition :process(reset,clk)
begin
if clr='1' then
p_state <=s0 ;
elsif rising_edge(clk) then
p_state <= n_state ;
end if;
end process transition;
next_state :process(N,D,p_state)
begin
case p_state is
when s0 =>
if N='1' then
tank_open <='0';
n_state <= s1;
elsif D='1' then
n_state <= s2;
tank_open <='0';
else n_state <= s0;
tank_open <='0';
end if;
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when s1 =>
if N='1' then
n_state <= s2;
tank_open <='0';
elsif D='1' then
n_state <= s0;
tank_open <='1';
else n_state <= s1;
tank_open <='0';
end if;
when s2 =>
if N='1' then
n_state <= s0;
tank_open <='1';
elsif D='1' then
n_state <= s0;
tank_open <='1';
else n_state <= s2;
tank_open <='0';
end if;
end case;
end process next_state;
end Behavioral;
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