Session three

http://www.bized.co.uk

Session 3

Prepared by
Alaa Salah Shehata
Mahmoud A. M. Abd El Latif
Mohamed Mohamed Tala’t
Mohamed Salah Mahmoud

Version 02 – October 2011
Copyright 2006 – Biz/ed


3
-ALU mini project discussion

Contents -Concurrent Statements
1-Assign Statement
2-Process
3-When-else
4-With-select

-Data Objects
1-Signals
2-Variables
3-Constants

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Session 3


Sel Operation
0000 Y<= a
ALU mini project discussion
0001 Y<= a+1
0010 Y<= a-1
0011 Y<= b
0100 Y<= b+1
0101 Y<= b-1
0110 Y<= a+b
0111 Y<= a+b+cin
1000 Y<= not a
1001 Y<= not b
1010 Y<= a AND b
1011 Y<= a OR b
1100 Y<= a NAND b
1101 Y<= a NOR b
1110 Y<= a XOR b
1111 Y<= a XNOR b

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Assignment

Process
Concurrent
When-Else

With-Select
Statements
Concurrent
IF
Statements
CASE
Sequential
FOR

WAIT

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Concurrent Statements Concurrency
We can consider any system to be consisted of many blocks each has a
specific function and work together concurrently (in parallel) to form the
whole function.

As VHDL is a Hardware Description Language so the default statements in
VHDL are those who are executed in parallel.
These statements are called Concurrent statements.

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Concurrent Statements Illustrating Example

In this Example, the value of x depends on a AND b, whenever a/b changes x will
change accordingly

Similarly the value of y will always change whenever c/d changes

It might happen that the value of x changes at the same time the value of y changes
 Both changes happen concurrently a
x
b
BEGIN
e
x <= a AND b;
c
y <= c AND d; y
END ;
e <= x AND y;
d

These assignment statements are concurrent, they can be written in any order
Think as Hardware
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Concurrent Statements 1- Assign Statements

Assignments relating outputs to inputs
Non Blocking Assignment <= is used
Assign statements can be written in any order.

architecture rtl of logic_gate is
begin
x <= a AND b;
y <= c OR b;
end rtl;

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Concurrent Statements 2- Process

Process allows writing sequential statements within concurrent environment

Process declaration

1 2 3
<Process Name> : PROCESS (sensitivity list)

4 process declaration; 5
Begin
sequential statements ; 6

7 1 <Process Name> : Optional Label
End PROCESS <Process Name> ; 2 PROCESS : Keyword
3 sensitivity list :
Signals inside it when make an event, the process trigger
4 process declaration
5 Begin : Keyword
6 Sequential statements
7 End : Process Suspend

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Concurrent Statements Transactions

Process (A,B)
begin
C <= A AND B ;
end process ;

A B C
0 1 0
1 0 0
1 1 1
The current value of A,B is read and the process is begun .
C <= A AND B ; causes a transaction
The value updated in C when the process suspend.
Transaction occurs when the process suspend

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Concurrent Statements Events

Process (A,B)
begin
C <= A AND B ;
end process ;

A B C
0 1 0
1 0 0
1 1 1

If the value of D is changed as a result of this transaction, an event occurs on this
signal.
Event occurs on signal when the value change

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Concurrent Statements Events vs Transactions
All signal assignment cause a transaction to be scheduled, but not every
transaction will result in an event on the target signal.

Note
Only an event on a given signal will cause a process to trigger if that signal is
included in its sensitivity list.

1-Signal A =0
2-Signal B changes to 0
3-process triggers on signal B event
4-Expression reevaluated
5-Transaction scheduled logic 0 on C
6-Process suspend
7-Tranasction applied to C
8-Value of C does not changed
9-No event on C only Transaction
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Session 2


• Find values of A,D and B
Process (A,B)
begin
A <= B + C ;
D <= B + E ;
B <= F + G ;
end process ;

Example
Signal Value
E 3
13
C 2
F 4
B 1
G 5

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Process (A,B)
begin
A <= B + C ;
D <= B + E ;
B <= F + G ;
end process ;

Signal Value Signal After first After Event
E 3 time this Process
Process Suspend
C 2 Trigger
F 4 A 3 11
B 1 D 4 12
G 5 B 9 9

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Concurrent Statements Modeling Concurrency
A VHDL simulator is event driven
- At any single point of discrete simulation time:
(1) All processes execute until they suspend
(2) Signals are updated
(3) Events on those signals cause more processes to resume execution
This is referred to as a delta cycle

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Concurrent Statements Modeling Concurrency

The event scheduler is the heart of the HDL behavioral environment
Each transaction is scheduled at its appropriate discrete time
Discrete time advances only when no more transactions are scheduled at the current time

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Concurrent Statements Connecting Processes

Processes and other concurrent operations are seen to take place at the same point in
discrete simulation time

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Multiple Processes

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Concurrent vs Sequential
 a suspended process is activated when any of signal of sensitivity list
changes.

 If we have multiple process and all is activated then all statement is
each process is executed sequentially .

 all process in any architecture are executed concurrently with each
other.

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Concurrent Statements 3- when-else

<target> <= <expression> when <condition>
else <expression> when <condition>
…
else <expression> ;

–LHS can be an internal signal or an output port
–RHS is an expression that operates on internal signal and/or input ports when the branch
condition is true
–Last “else” branch covers all missing conditions

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• 4X1 Multiplexer using when-else

Example
14

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4X1 MUX (when-else)

Architecture behave of mux_when is
Begin
F <= a when sel = "00" else
b when sel = "01" else
c when sel = "10" else
d when sel = "11" else
„Z‟;
-- This is one statement with semicolon at the end only
End behave ;

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Concurrent Statements 4- With – select - when
With <select_signal> select
<target> <= <expression> when <value>,
<expression> when <value>,
….
< expression> when others;

–<select_signal> can be an internal signal or an input port
–<target> can be an internal signal or an output port
–<value> constants representing one of possible <select_signal> values.
–“When others” is a must if not all values of <select_signal> are covered

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• 4X1 Multiplexer using with-select-when

Example
15

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4X1 MUX (With – select - when)

Architecture behave of mux_with is
Begin
With sel select
F <= a when "00",
b when "01",
c when "10",
d when "10",
„Z‟ when others;
-- needed to cover missing “sel” values
End behave ;

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• Simulate 2X4 Decoder and 4X2 Encoder
Using When-else and With-Select-When

lab
2

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With <select_signal> select
<target> <= <expression> when <value>,
<expression> when <value>,
….
< expression> when others;
------------------------------------------------------------------------------------

<target> <= <expression> when <condition>
…
else <expression> ;

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2x4 Decoder (when-else)

Architecture behave of decoder2x4 is
Begin
F <= "0001" when a = "00" else
"0010" when a = "01" else
"0100" when a = "10" else
“1000" when a = "11" else
“ZZZZ";
End behave ;

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4X2 Encoder (when-else)

Architecture behave of encoder2x4 is
Begin
F <= “00" when a = “1000" else
"01" when a = “0100" else
"10" when a = “0010" else
"11" when a = “0001" else
“ZZ";
End behave ;

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Session 3


2x4 Decoder (With – select - when)

Architecture behave of decoder4x2 is
Begin
With a select
F <= "0001" when "00",
"0010" when "01",
“0100" when "10",
“1000" when "11",
“ZZZZ" when others;
End behave ;

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4X2 Encoder (With – select - when)

Architecture behave of encoder2x4 is
Begin
with A select
F <= "00" when “1000",
"01" when "0100",
"10" when “0010",
"11" when “0001",
“ZZ" when others;
End behave ;

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Questions
Session-3

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Break
Be ready for the second part of this session

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Data Objects

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Data Objects

-Data Objects are the Value holders
-VHDL offers different data objects:
1-Signals Used to model connections
Signals can be:
External Signals
Internal Signals
2-Variables Used for computations

3-Constants Used to store values that can’t be changed during simulation time

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Session 3


Data Objects 1-Signals

Signals Used to model connections, signals can be divided into two main types :

External Signals (Ports)
Used as an interface for the Entity to the outside world
pass values in and out the circuit, between its internal units.
Declared in Entity
All PORTS of an ENTITY are signals by default

Internal Signals
Used inside the Architecture to connect different logic parts
Declared in Architecture
Represents circuit interconnects (wires)

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External Signal declaration

entity <entity_name> is Example
port ( ENTITY AND_GATE IS
<port_name> : <mode> <type>; port ( a,b : in BIT;
----- C : out BIT
<port_name> : <mode> <type> );
); END ENTITY AND_GATE ;
End <entity_name> ; NAND_GATE ;

Internal Signal declaration

architecture <arch_name> of <entity_name> is
-- architecture declarations
signal <sig_name> : <sig_type>;
begin Example

End <arch_name> ; SIGNAL control: BIT ;
SIGNAL y: STD_LOGIC_VECTOR(7 DOWNTO 0);

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Session 3


Assignment Operator
Assigned using “<=”
Non-Blocking Assignment
Example
inp_x <=“0000”;
sig_1 <=„1‟;

Behavior
Used in Concurrent or Sequential
Outside a process
its value is updated when their signal assignment is executed.
Inside a process
its value is updated after the process suspends
only last assignment to signal listed inside the process is effective .

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Objective
-Be familiar with signals declaration
-Using Signals inside and outside the process

Example
16

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A=1 ,B=1 ,C=1, D=2  C changes from 1 to 2
What is the values of A,B and C ?

Process (C,D)
Begin
A<=2; A=
B<=A+C;
A<=D+1;
B=
C<=B+A; C=
End process;

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Session 3


A=1 ,B=1 ,C=1, D=2  C changes from 1 to 2
What is the values of A,B and C ?

Process (C,D)
Begin
A<=2; A=3
B<=A+C;
A<=D+1;
B=3
C<=B+A; C=2
End process;

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Objective
-Be familiar with signals declaration

Exercise
2

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Session 3


signal signal1: integer :=1; -- initial value
begin
process (………)
begin
……………
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
……………
end process;

Find the value of result?

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-- All Signals have the uninitialized value ‘U’
-- Force A = '1' then force A='0' then A='1'
library IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity signal_lab is
port( A: in std_logic
);
End signal_lab;

Architecture behave of signal_lab is
Signal Z,G,F,X : STD_LOGIC;
begin
process (A)
Begin A 1 0 1
Z <= A;
G <= '1'; Z ? ? ?
F <= G;
X <= F; G ? ? ?
G <= '0';
Z <= G; F ? ? ?
end process ; X ? ? ?
end behave;

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library IEEE;

);
End signal_lab;

begin
process (A)
Begin A 1 0 1
Z <= A;
G <= '1'; Z U 0 0
F <= G;
X <= F; G 0 0 0
G <= '0';
Z <= G; F U 0 0
end process ; X U U 0
end behave;

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Session 3


library IEEE;

);
End signal_lab;

begin
process (A)
Begin
Z <= A;
G <= '1';
F <= G;
X <= F;
end process ;
G <= '0';
Z <= G;
end behave;

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library IEEE;

);
End signal_lab;

begin
process (A)
Begin Any statement written out side
Z <= A;
G <= '1';
process is concurrent statement ,
F <= G; It execute concurrently with process
X <= F;
end process ;
G <= '0'; G and Z has two values at same time
Z <= G; value of A and value of G.
end behave;

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Session 3


Data Objects 2-Variables
Variables are used for computations
Represent only local information
Declared inside a process
can only be used inside a PROCESS (in sequential code).

Variable declaration
architecture behave of MPU is
begin
process(…)
variable x, y : std_logic ;
variable intbus : std_logic_vector(7 downto 0);
begin
.
. .
end process ;
.
.
end behave;
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Session 3


Data Objects 2-Variables

Assignment Operator
Assigned using “:=”
Blocking Assignment

Example
var_x :=“0000”;
var_1 :=„1‟;

Behavior
its value can not be passed out directly
its update is immediate, so the new value is used in the next line of code.
As long as signal and variable have same type they can be assign to each
other .

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Objective
-Be familiar with variable declaration
-Using variable inside the process

Example
17

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Session 3


process(……)
variable variable1: integer :=1;
begin
………
variable1 := variable2;
variable2 := variable1 + variable3;
variable3 := variable2;
RESULT <= variable1 + variable2 + variable3;
………..
end process;

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Session 3


Objective
-Be familiar with variables declaration

Exercise
3

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Session 3


-- Force A = "001"
library IEEE;

port( A : in std_logic_vector(2 downto 0)
);
End signal_lab;

begin
process (A)
Variable Z,G,F,X : std_logic_vector(2 downto 0);
Begin
G := A + A;
F := G + A;
X := G + F;
Z := X + F;
end process ;
end behave;

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Session 3


Data Objects Initialization

made when we declare the variable or the function
using :=
signal sigbus : std_logic_vector(7 downto 0) := "01011110";
variable z : std_logic := '1';
variable varbus : std_logic_vector(3 downto 0) := "0001";

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Session 3


2-Initializations

Signals inside your design should have initial values
Synthesis tools ignore initial values specified for a variable or a signal in its declaration.
The best way for initialization is to initialize the signals when the reset is active.

If reset = „1‟ then
sig_1 <= „0‟ ;
sig_2 <= “00000”;
sig_3 <= “10101010”;
out_1 <= “00”
elsif ris……
………

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Session 3


Data Objects Signal vs Variable
Signals Variables
Declaration Internal : Inside Process Declaration
Inside Architecture Declaration
External :
Inside Port entity
Assignment Non-Blocking Assign <= Blocking Assign :=
Initialization := :=
Update After the process suspend Immediately
Scope Seen by the whole code Local onside process

Can be used in either type of code, Can only be used inside
concurrent or sequential. a sequential code
UTILITY Represents circuit interconnects Represents local information
(wires)

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Data Objects Object Scope
-Ports are signals and declared at the top level (entity)
-Within the architecture, local signals are declared
-Within the process, local variables can be declared

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Data Objects 3-Constants

A constant can have a single value of a given type and cannot be changed during
the simulation.

Constant Declaration
constant <con_name> : <data_type>; := <con_value>;

Constants can be declared at the start of an architecture and can then be used
anywhere within the architecture.

Constants declared within a process can only be used inside that specific a
Process.

Example
CONSTANT set_bit : BIT := '1';

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Objective
-General Example

Example
18

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Session 3


Calculate the values of var1, sig1& Q

process (a,b)
variable var1: integer;
begin
var1 := a + b;
sig1 <= var1;
Q <= sig1;
end process;

Var1 sig1 Q Exercise
A=1 3 4 6
B=2
4
A=2 During process

B=3 Process suspend

A=5 During process
B=2 Process suspend

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Session 3


Calculate the values of var1, sig1& Q

Var1 sig1 Q
A=1 3 4 6
B=2
A=2 5 4 6 During process

B=3 5 5 4 Process suspend

A=5 7 5 4 During process
B=2 7 7 5 Process suspend

process (a,b)
variable var1: integer;
begin
var1 := a + b;
sig1 <= var1;
Q <= sig1;
end process;
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Session 3


• Do one of the Previous Exercises on ModelSim
to sense the difference between signals and variables

lab
4

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Session 3


Assignment
Session-3

Study the three sessions well

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Session 3


Download Session 3 material

Session 3.pdf

Ask for the material through mail
start.courses@gmail.com

Facebook group
start.group@groups.facebook.com

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Session 3


Questions
Session-3

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Session 3


Take Your Notes
Print the slides and take your notes here

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See You Next Session

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Session three

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