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3D-IC Designs require 3D tools
- 1. Tools and Methodologies for 3D-IC Design AJ Incorvaia Vice President, Silicon Package Board Group May, 2012
- 2. Where we are today – Industry View Paradigm Shift from 2D SoCs 3D stacks Moving to vertical stacking using TSVs provides Reuse of older process node (IP reuse/ heterogeneous int.) Higher performance Low Power Reduced Cost 2 © 2012 Cadence Design Systems, Inc. All rights reserved.
- 3. Short, medium and long term path to 3D-IC EDA work starts at least 3-4 years earlier Si Partitioning Memory Cube Logic + memory Wide IO + Logic High with TSV with TSVs w/ 2.5D TSV with TSVs performance Interposer computing Interposer • MARKET : Server •MARKET : Mobile, Tablet, gaming • MARKET : CPU, • Market : FPGA & Computing • MARKET : GPU, processors MCMs etc Gaming Console • Xilinx in 2010 • IBM & Micron • ST-E /LETI •ST-E /LETI •Altera in 2012 testchip • ST testchip in WIOMING in 2011 2010 WIOMING in 2011 • 2011-2012 • 2012-2013 • 2013-2014 • 2013-2014 • ~ 2015 SHORT MEDIUM LONG Standards, Ecosystem, Cost 3 © 2012 Cadence Design Systems, Inc. All rights reserved.
- 4. So what changes with 3DIC in EDA world? Revamped EDA requirements New Layout Rules (e.g. alignments) New Layout Layer (e.g. Back Side RDL) New Layout & Electrical Feature (e.g. TSV) New Floorplanning & Blockage Rules (TSV) Thermal & mechanical constraints New Models, Rules Courtesy : Qualcomm 4 © 2012 Cadence Design Systems, Inc. All rights reserved.
- 5. 3DIC Design Flow Challenges System Level Exploration 3D Floorplan – Optimized power New 3DIC Design Flow Plan and TSV/Bump locations Implementation Challenges Placement, Optimization and Routing Extraction and Analysis Manage Power, Thermal and SI DFT for 3DIC Stack & Diagnostics Silicon Package Co-Design 5 © 2012 Cadence Design Systems, Inc. All rights reserved. 5
- 6. 3D Stack Die Editor Die to Die Co-Design Flow Open access enables interaction between analog and digital 3D Floorplan – Optimized power Plan and TSV/Bump locations Custom Editing Typical 3D-IC Design Flow TSV /Bump RDL Routing 3D IR Drop Analysis Silicon Interposer IC-Package Co design flow 3D Thermal Maps Back-side Bump Management Silicon Interposer 6 © 2012 Cadence Design Systems, Inc. All rights reserved.
- 7. Partnering with the Ecosystem Designers: Analysis Driven Design & Stacking Methodology System House: Multi-Die Integrated Package Prototyping Foundry & IDM : Rules, Stacking Layers & Modeling Everyone : DFM/Yield/Reliability And Redundancy 7 © 2012 Cadence Design Systems, Inc. All rights reserved.
- 8. Collaboration with Foundry Partners 8 © 2012 Cadence Design Systems, Inc. All rights reserved.
- 9. Foundation required to enable 3D-IC Custom, Digital & Package solutions need to understand 3D constructs Modeling and database infrastructure to support TSVs, Micro bumps, backside metals Seamless Digital, Custom and Package co-design Comprehensive solutions needed to span all aspects of IC design, including digital design, analog and custom design and packaging co-design Ecosystem partnerships Ecosystem is still developing, so partnerships are needed to develop methodologies and proof points between the various stakeholders 9 © 2012 Cadence Design Systems, Inc. All rights reserved.
- 10. Industry Example: 2.5D Using Silicon Interposer Source: RTI 3D conference 2010 proceedings 10 © 2012 Cadence Design Systems, Inc. All rights reserved. 10 © 2011 Cadence Design Systems, Inc. All Rights Reserved
- 11. Industry Example: 3D IC Stack with WideIO 11 © 2012 Cadence Design Systems, Inc. All rights reserved.
- 12. Industry Example: 3D IC Stack with WideIO 12 © 2012 Cadence Design Systems, Inc. All rights reserved.
- 13. Summary: Cadence silicon-proven 3D-IC solution Plan Implement Test Verify • Cadence is the technology leader providing complete and integrated 3D- IC solution – Plan->implement->test->verify – 1st to market wide I/O memory controller • Developed in close partner- collaboration for 5+ years with leading foundries and customers • Multiple 3D-IC tapeouts – Multiple testchip experience: Memory over logic (28 nm), logic over analog, logic over Logic, 3-stack dies – Production design tapeouts 13 © 2012 Cadence Design Systems, Inc. All rights reserved.
- 14. 14 © 2012 Cadence Design Systems, Inc. All rights reserved.
Notes de l'éditeur
- It is infact a paradigm shift.. We are use to thinking 2D but the need for performance, power, and smaller footprints Are pushing us to utilize the 3rd dimension as well. Reasons….CMOS Scaling has reached its limit Physics will DEMAND that memory and analog functions DO NOT migrate to 22 nm together or even 16 and force our industry to combine heterogeneous die. Keep in mind that 3D will reduce the need to invest huge R&D efforts into developing "can do all" processes for SoCs with high-speed logic, precision analog, cost-effective large eDRAMs, and other features.Mobility Is Key From chipset to systems : As an example, let’s take a look at the mobile device industry. Clearly the convergence of mobility, communications and computing is the key trend driving the industry.This is what our consumer ask for…Right !! Thin gadgets, Lots of features, Their toy to run fast and at the same time be affordable “to them” : Small, Simple, Blazing Fast & Cheap all at the same time.Time to market is key : it is costly to build “can do all processes” and more and more IP reuse trends are becoming obvious. Trend is reusing what can be used with minimal add ons to tailor it to a different application, different marker – 80-20 rule applies…3D SoC integration of heterogeneous technologies is what is driving 3D ICs