3. The Serial Link ‐ Background
Tx Interconnect Receiver
Driver
Target: To transmit serial data over a given interconnect and receive it with a desired BER.
We will discuss the following serial link related issues:
Serial link data frequency content
Serial link components and what influences them:
– Tx driver
– Interconnect
– Receiver
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4. Frequency Content of a Serial Signal – Square Wave
An “ideal” square wave can be constructed of sinusoidal components of odd
multiplications of the signal’s “main” frequency.
What is the frequency content of an 8‐10 encoded bit stream?
Fastest symbol is 1010…
Slowest symbol is constructed of 5 consecutive bits. First Harmonic resides between Fb/10
Fb/2 (there may be even lower frequencies corresponding to repeating data strings.)
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5. Frequency Content of a Serial Signal
An “Ideal” Interconnect
What interconnect will not change the signal shape except for the amplitude?
We said that:
The serial data consists of different length of consecutive bits wide symbol
frequency range
Each symbol incorporates a set of sinusoidal frequencies
What would be the “ideal” interconnect description in the frequency domain?
A flat insertion loss response over frequency with a constant group delay over
frequency (linear phase)
This interconnect is not practical
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6. The Interconnect
A Well‐designed Physical Interconnect
• Due to physical characteristics of the material
a “well designed” printed circuit board trace
frequency response shows linear loss (in db
scale) and linear phase behavior.
• Frequency content of the first harmonic is
from FB/(2*longest bit stream) to Fb/2
(Fb/10 to Fb/2 in 8‐10 encoding) ISI
• Other interconnect characteristics /
phenomena will be discussed later in this
presentation
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10. The Serial Link – Advanced Phenomena
Tx Interconnect Receiver
Driver
The impact of differential inner pair skew (the difference in delay between the
positive and negative interconnect paths).
Multiple reflections – signal degradation due to the presence of multiple
discontinuities along an interconnect and the main difference between a single
reflection and multiple reflections.
Passive interconnect as a DCD amplifier – what happens to a signal that has a
certain amount of duty cycle distortion when traveling through a high speed
interconnect.
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12. Differential inner pair skew – Analysis
Looking at the impact of skew on differential harmonic signals one can observe
that:
The main impact of skew would be seen on the signal amplitude. The larger the
skew (in terms of UI) the larger the amplitude degradation.
The harmonic signal width is not influenced, rather the ideal sampling point is
shifted.
Since high frequency symbols (such as 1010…) have small UI width, inner pair skew
will degrade their amplitude by a larger amount compared to lower frequency
symbols (such as 111000…). This will introduce ISI.
In the case of short reach interconnects, the signal may still have a portion of
higher harmonies amplitudes signals rise/fall will be highly impacted.
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15. Reflections ‐ Observations
ZL Z 0
reflected : L
ZL Z 0
ZL Z 0 2ZL
Transfered :TL 1 L 1
ZL Z 0 ZL Z 0
The reflected portion can be positive or negative
The transferred portion can only have non‐negative magnitudes
The transferred portion will accumulate phase as it advances through the reflecting object
(such as a via, a trace with different impedance, etc.)
A wave advancing through an interconnect accumulates phase (the interconnect has a
propagation delay).
An advancing wave may be attenuated with an amount related to the medium characteristics
(dielectric loss coefficient, mechanical dimensions that influence the skin effect, copper
surface roughness).
Advancing and reflected waves may interact forming interference ( – )התאבכותThis effect will
occur only in the presence of more than a single reflection multiple reflections effect.
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17. Multiple reflections – simulated results
Two Differential vias (G‐S‐S‐G) with via stubs structure.
Traces (lossless) connecting the two structures.
Reflected signal bounces back and forth to create interference.
Loss will lower the interference amplitude.
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18. Multiple reflections – simulated results
Multiple reflections causes transfer to introduce ripple (usually referred to as insertion loss
deviation – ILD) – why?
The reason for optimizing return loss
Insertion loss
Return loss
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20. Duty Cycle Distortion – Simulation results
Driver has a minimal
pulse width of
86.8psec ‐ 10psec
degradation due to
DCD.
Signal at the
interconnect Far‐End
has a 16psec
degradation due to
DCD
DCD was increased as
a result of passing
through the
interconnect.
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