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TRACK F: FPGA Prototypes and Emulators – a Symbiotic Approach/ Ilan Harel
1. May 1, 2013 1
FPGA Prototypes and Emulators
– a Symbiotic Approach
May 1, 2013
Ilan Harel
Networking Division
Intel
2. May 1, 2013 2
FPGA Prototypes and Emulators
– a Symbiotic Approach
May 1, 2013
Presented by Stas Cherkassky,
Leonid Yuhananov
3. May 1, 2013 3
Agenda
May 1, 2013
• Intel’s Networking Division
• The World of ASIC Prototyping
• Big Box Emulation
• Leveraging both techniques
• Summary
• Q/A
4. May 1, 2013 4
Intel’s Networking Division
May 1, 2013
• ND creates high speed
Ethernet Controllers
• ASIC is a pipe:
• PCIE on one side, Ethernet
LAN on the other
• Transfer packets from side
to side
5. May 1, 2013 5
Prototyping in development flow
May 1, 2013
RTL Coding &
Verification
FAB Post-Si
RTL drop to
emulation
Tape Out
Prototype
Silicon
6. May 1, 2013 6
Photo’s of HW examples
Commercial “Black Box”Commercial “White Box”Custom FPGA prototypes
7. May 1, 2013 7
FPGA Box Setup
May 1, 2013
Host
PCIe LAN
Link Partner
DUT @ FPGA
Test Controlling
System
8. May 1, 2013 8
BBE In-Circuit Emulation setup
May 1, 2013
Host
PCIe LAN
Link Partner
DUT @ Emulator
Test Controlling
System
9. May 1, 2013 9
BBE Acceleration setup
May 1, 2013
Co-sim
Host
SW
link
DUT @ Emulator
10. May 1, 2013 10
FPGA prototyping challenges
May 1, 2013
• Design Size
• FPGA partitioning
• Logic trimming
• Si to FPGA conversion
• Frequency
• Clock tree (gates, switches)
• Development cycle
• Long synthesis time
• Poor visibility
• FPGA set of tools
11. May 1, 2013 11
Big Box Emulator prototyping
challenges
May 1, 2013
• Cost : ~ 10X [FPGA cost per gate]
• Speed: usually slower than FPGAs
• Mobility: Heavy and require vast lab
infrastructure.
12. May 1, 2013 12
Leveraging both techniques
May 1, 2013
13. May 1, 2013 13
The ramp-up vehicle
May 1, 2013
• FPGA prototype initial ramp up takes
much time: compilation, synthesis, timing
convergence, debug
Use the Emulator to bring up the FPGA model
Ramp-up ~3-5X faster
14. May 1, 2013 14
The satellite concept
May 1, 2013
SV
SV SW
SW
SW
FW
FW
FW
EM
EM
SW
SW
RTL
RTL
SW
SW
Big box
emulator
SW,SV,FW
Development
Debug
15. May 1, 2013 15
The satellite concept
May 1, 2013
• FPGA prototypes are
affordable. they are
part of SW/FW/SV
development platform
S
V
S
V
S
W S
W
S
W
F
W
F
W
F
W
E
M
E
M
S
W
S
W
RTL
RTL
S
W
S
W
Big box
emulator
SW,SV,FW
Development
Debu
g
Once bugs are found, debug with Emulator
Once reproduced – 5x faster debug
16. May 1, 2013 16
Complete Full Chip prototyping
May 1, 2013
• FPGAs prototypes provide most of the logic
but not all of it.
• Main reasons are their limited capacity;
difficulty in imitating clock tree and limited
connectivity between FPGAs
use Emulator to prototype the entire ASIC.
17. May 1, 2013 17
RTL Models
May 1, 2013
Silicon RTL
FPGA RTL for FPGA
box
FPGA RTL for
Emulator
Silicon RTL for
Emulator
18. May 1, 2013 18
Results
May 1, 2013
• Initial ramp up took 10 days
• Emulator speed = 0.25X FPGA-box speed
• Emulator compilation of FC = 0.2X of FPGA
• Visibility = entire design for ~400K cycles
• 80% of bugs found over FPGA were successfully
reproduced, debugged and solved over the Emulator
• Average time invested in solving issues over Emulator
is ~5X shorter than over FPGA estimate
19. May 1, 2013 19
Summary
May 1, 2013
• The combination provides a
powerful solution which leverages
both Emulator and FPGA strengths
• Automation in moving from one
model type to the other is a key to
this technique
20. May 1, 2013 20
For additional questions:
May 1, 2013
• Emulation: Ilan Harel
(ilan.harel@intel.com)
• Emulation: Leonid Yuhananov
(leonid.yuhananov@intel.com)
• Acceleration: Stas Cherkassky
(stas.cherkassky@intel.com)
22. May 1, 2013 22
Special forces development vehicle
May 1, 2013
• BIST pattern development
• GLS
• PHY emulation
23. May 1, 2013 23
Intel Confidential- Internal Use Only
Differentiation: 3 types of emulators
•Commercial “black box” Emulators:
•Can accommodate large designs (currently ~5M100M+ gates)
•Low-level details of emulator HW design (FPGA/routing) is hidden from users: “Black box”
•All required tools/flow provided by the single emulator vendor
•Speed: 100Khz-1Mhz ; platform cost: 0.5-2M$
•Commercial “white box” Emulators:
•Realistically, best for mid-sized designs (Currently ~<250M gates)
•User must deal with lower level/FPGA HW details internal to the emulator However usually wrapped
with SW: “white box”
•Often, HW/SW from several vendors make up the complete solution.
•Speed: <10Mhz ; platform cost: 100-200K$
•Custom Designed FPGA Prototype
Boards:
•Best for smaller designs (currently ~< 20M gates)
•User owns designing the emulation platform and manages all details.
•The fastest emulation technology with lowest cost/system.
•Speed: ~60Mhz ; platform cost: ~7-14K$
