MAPLD 2009 Presentation of a universal reconfigurable multi processor hardware platform for space

1. Universal Reconfigurable Processing Platform for Space Presented by Dorian Seagrave Gordonicus LLC

8. MAPLD 2009 Gordonicus LLC LEON3FT PROCESSOR & MEMORY LEON3FT Aeroflex UT699 2MByte SRAM (Internal EDAC ) 32KB PROM 1GByte SDRAM (Reed Solomon) 4GByte FLASH Actel RTAX TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg 52.8 MIPS 4GByte FLASH

10. MAPLD 2009 Gordonicus LLC Xilinx QV4 FX60 PPC 405 PPC 405 Xilinx QV4 FX60 XILINX PPC405 PROCESSORS & MEMORY PPC 405 512MByte SDRAM 200Mbps SpaceWire(4) Dual Xilinx QV4 FX60 PPC 405 700 DMIPs TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO) 512MByte SDRAM 512MByte SDRAM 512MByte SDRAM LEON3FT Aeroflex UT699 Based on Heritage Architecture Implementation

14. CompactPCI MIL-STD-1553 A/B LEON3FT Console Port MAPLD 2009 Gordonicus LLC

15. SpaceWire Ports MAPLD 2009 Gordonicus LLC LEON3FT SpW Router 5 Port SpW Router 5 Port RTAX 200Mbps Configurable 200/100/50 Mbps 200Mbps Front Panel Conn. Thru-hole Jumpers F R O N T P A N E L C P C I P 2 Xilinx 200Mbps 10 Front Panel 4 Backplane 2 Backplane via Jumpers 200Mbps Configurable

17. 73 User Defined I/O MAPLD 2009 Gordonicus LLC LVDS OR RS422 LEON3FT F R O N T P A N E L C P C I P 2 Xilinx 39 User Defined I/O LVDS OR RS422 LVDS OR RS422 LVDS OR RS422 LVDS OR RS422 Sync / Async Serial IF I2C 1 Wire Protocol 10 Bi-Dir User Defined I/O 2 GPIO ACTEL 12 User Defined I/O

20. MAPLD 2009 Gordonicus LLC

21. 512MB 512MB 512MB MAPLD 2009 Gordonicus LLC Application RTAX SpW Router DownLink0 512MB SpaceWire SpaceWire SpW Router DownLink1 MissionCrd0 MissionCrd1 MissionCrd2 MissionCrd3 PPC 405 uP PPC 405 uP PPC 405 uP LEON3FT PPC 405 uP

23. Future …. MAPLD 2009 Gordonicus LLC Xilinx SIRF V5 Xilinx SIRF V5

24. Next Effort MAPLD 2009 Gordonicus LLC LEON3FT 16 MBytes EEPROM 8 Port SpW Router 16 GBytes FLASH 1 GByte SDRAM 1553 3U cPCI