An Overview on Programmable System on Chip: PSoC-5
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3. Introducing PSoC® 3 and PSoC® 5: One Platform, Three Architectures PSoC Creator™ - Revolutionary Integrated Development Environment for PSoC 3 and PSoC 5 PSoC 1 - Performance, programmability and flexibility with a cost-optimized 8-bit M8C CPU Subsystem PSoC 3 - Single-cycle, pipelined 8-bit 8051 and a high-performance configurable digital system for unmatched analog and digital bill-of- materials integration PSoC 5 - 32-bit 80 MHz ARM Cortex-M3 CPU for larger, more complex applications with additional flash, SRAM and off-chip memory access including RTOS support
Welcome to the training module on Cypress’s Programmable system on chip: PSoC 5
In this modules we will study the Architecture of PSoC5 devices.
Cypress semiconductor has three architecture based Programmable system on chip, PSoC 1 is based on M8C Architecture which is Cypress proprietary based and PSoC 3 is based on industry standard 8051 architecture based, and PSoC 5 is based on 32-bit Cortex-M3 CPU.
This slide compare the performances between PSoC 1, PSoC 3 and PSoC 5. It brings the PSoC design methodology to high precision analog & high performance 8-, 16- and 32-bit markets. PSoC 1 is M8C based architecture with 4 MIPS and 32KB of flash memory. PSoC 3 is based on the 8051 which has 33 MIPS processing speed with 64KB of flash and finally PSoC 5 is based on ARM Cortex-M3 and its processing speed is 100 DMIPS with 256KB of flash memory.
PSoC is the programmable embedded SoC integrating configurable analog and digital peripheral functions, memory and a microcontroller on a single chip. PSoC 5 is a true programmable embedded system-on-chip integrating configurable analog and digital peripheral functions, memory and a microcontroller on a single chip. There are 4 main components of the PSoC Platform: CPU Subsystem, Digital Subsystem, Analog Subsystem and Programmable Routing and Interconnect. Universal Digital Blocks Implement features in hardware that reduce CPU processing requirements, lowering power consumption On-board DMA Controller Direct memory transfer between peripherals offloads CPU operation, lowering power consumption Integrated Analog, Digital and Communication Peripherals Reduce external component counts and lower overall system power consumption Precise CPU frequencies PLL allows 4,032 different frequencies; tunable power consumption
PSoC 5 is a true programmable embedded system-on-chip integrating configurable analog and digital peripheral functions, memory and a microcontroller on a single chip, its architecture boosts performance through: Integrated high-precision 20-bit resolution analog, Ultra low power with industry’s widest voltage range, Programmable PLD-based logic, 32-bit ARM® Cortex™-M3 CPU up to 80 MHz.
Eight 16-bit clock dividers generate digital system clocks for general use in the digital system, as configured by the design’s requirements. Digital system clocks can generate custom clocks derived from any of the seven clock sources for any purpose. Examples include baud rate generators, accurate PWM periods, and timer clocks, as well as many others. If more than eight digital clock dividers are required, the Universal Digital Blocks (UDBs) and fixed function Timer/Counter/PWMs can also generate clocks. Four 16-bit clock dividers generate clocks for the analog system components that require clocking, like ADCs and mixers. The analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. This is done to reduce analog system noise.
Universal Digital Block is capable of Intelligent routing Efficiency of the UDBs (part/pieces of each UDB can be used sep.) Custom logic Standard peripherals + custom logic It has ~500 - 700 gates per UDB, 24 UDBs in the larger chips, p rovides nearly all of the features of a UDB based timer, counter, or PWM in an area optimized peripheral. Each block may be configured as either a full featured 16-bit Timer, Counter, or PWM.
Provides nearly all of the features of a UDB based timer, counter, or PWM in an area optimized peripheral. PSoC Creator provides easy access to these flexible blocks. Each block may be configured as either a full featured 16-bit Timer, Counter, or PWM. It has Flexibility features like: Clock, Enable, Reset, Capture, Kill from any pin or digital signal on chip. Independent control of terminal count, interrupt, compare, reset, enable, capture, and kill synchronization.
The configurable analog system uses separate modules The PSoC3/5 architecture has a huge portfolio of analog IP. Exact configuration depends on the product family. It has 20-bit DelSig samples at 180 samples per second.
This slide talks about routing and interconnects. The device has 3 types of I/Os, namely: general purpose I/Os, Serial I/Os and USB I/Os. GPIOs can be conneted to any peripheral routing. There are 8 different configurable drive modes.
Tail Chaining allows the processor to transit from the currently executing ISR directly to another pending ISR without having to spend the normally required cycles to restore state back to main and then to store the state again to get back to the other pending interrupt.
These are the various PSoC power modes. They are: Active Mode, Sleep Mode and Hibernate Mode.
PSOC devices have dedicated communication peripherals like full speed USB device, full CAN 2.0b, I2C master or slave.
Cypress PSoC 3 and 5 devices can be programmed using the PSOC Creator. This IDE has the same industry look and feel. It’s design flow involves configuration of the components, developing hardware design, writing code, compiling, building and programming the hex file to the device.
CY8C-KIT-001 is the PSoC development kit. The board also has a prototyping area containing a small bread board complete with I/O port sockets nearby, multipurpose LEDs, mechanical push buttons, and a multipurpose variable resistor. Three capacitive sensing elements: two buttons and a 5 segment slider are included on the board allowing evaluation of CapSense™ touch-sensing applications. The board has four GPIO expansion slots around the periphery providing expandability of the I/O to external boards.
The CY8CKIT-001 kit contains a main PSoC development board, and three processor module boards for the different architectures: PSoC 1, PSoC 3 and PSoC 5 devices. It also includes a MiniProg3 debug and evaluation device, prototyping cable kit, a USB cable, a 12V AC power adapter, and both PSoC Creator™ and PSoC Designer™ software. The CY8C-KIT-001 PSoC® Development Kit provides you a common development platform where you can prototype and evaluate different solutions using any one of the PSoC1, PSoC3, or PSoC5 architectures. This guide and kit gives you a practical understanding of PSoC technology. In addition, the kit gives several example projects with step-by-step instructions to enable you to easily get started developing PSoC solutions.
The PSoC 5 FirstTouch™ Starter Kit is designed to introduce you to the PSoC programmable system-on-chip design methodology and Cypress's new PSoC 5 architecture. This full-featured starter kit ships with an array of sensors, I/O's, projects & software to quickly get you up to speed with PSoC Creator and our powerful design methodology so you can easily evaluate PSoC.
This page gives the features and kit content of CY8CKIT-014 Kit it has different types of interface like Accelerometer, Thermistor Proximity sensor
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