MPC854XE: PowerQUICC III Processors
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An overview study on PowerQUICC III Processors
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MPC854XE: PowerQUICC III Processors
- 4. MPC8548E Block Diagram MPC8548E Block Diagram
- 5. e500 Core Complex Block Diagram e500 Core
- 8. System Clock / PCI Clock System Clock / PCI Clock
- 14. DUART UART Block Diagram • Receive and transmit buffers. • Clear to send (CTS) input port and request to send (RTS) output port for data flow control. • 16-bit counter for baud rate generation. • Interrupt control logic.
- 20. Enhanced Three-Speed Ethernet Controllers eTSEC Block Diagram
- 21. MPC8548E Applications VPN Access Router Enabled by PCI Express and Ethernet RAID Controller Application Using MPC8548E
Notes de l'éditeur
- Welcome to the training module on MPC 854X device. This training module introduces the features of e500 Core and supporting devices, its peripheral functions incorporated in this device.
- Key features include256KB L2 cache, integrated security, 64-bit DDR1/2 scaling up to 400 MHz data rate, 32-bit PCI, 4-bit Serial RapidIO or 4-bit PCI Express, and two Gigabit Ethernet interfaces. With clock frequencies scaling from 800 MHz to 1 GHz, this cost-effective device is ideally suited for a wide range of general-purpose embedded control applications, such as robotics, discrete manufacturing and process manufacturing control.
- The processors are designed to offer clock speeds scaling up to 1.333 GHz with headroom for 1.5 GHz. They combine the powerful processor core, enhanced peripherals and high-speed interconnect technology to balance processor performance with I/O system throughput. processors offer a wide range of high-speed connectivity options, including Gigabit Ethernet, Serial RapidIO® technology and PCI Express. Support for these high-speed interfaces enables scalable connectivity to network processors and/or ASICs in the data plane while the PowerQUICC III handles complex, computationally demanding control plane processing tasks. These processors also feature next-generation double data rate (DDRII) memory controller, enhanced, Gigabit Ethernet support, double precision floating point and integrated security engines that support the Kasumi algorithm needed 3G wireless security.
- Here is a block diagram of the processor core complex that shows how the functional units operate independently and in parallel. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs).
- The MPC8548E contains an internal 512-Kbyte memory array that can be configured as memory-mapped SRAM or as a look-aside L2 cache. The array can also be divided into two arrays, one of which may be used as cache and the other as SRAM. The memory controller for this array connects to the core complex bus (CCB) and communicates via 128-bit read and write buses to the e500 core and the MPC8548E system logic.
- Memory controller signals are grouped as Memory interface signals, Clock signals, Debug signals. Signals is organized into the following sections: • Overview of signals and cross-references for signals that serve multiple functions, including two lists: one by functional block and one alphabetical • List of reset configuration signals • List of output signal states at reset
- The MPC8548E takes a single input clock, SYSCLK, as its primary clock source for the e500 core and all of the devices and interfaces that operate synchronously with the core. The SYSCLK input (frequency) is multiplied up using a phase lock loop (PLL) to create the core complex bus (CCB) clock (also called the platform clock). The CCB clock is used by virtually all of the synchronous system logic, including the L2 cache, and other internal blocks such as the DMA and interrupt controller. The CCB clock also feeds the PLL in the e500 core and the PLL that create clocks for the local bus memory controller
- The e500 core complex supports demand-paged virtual memory as well other memory management schemes that depend on precise control of effective-to-physical address translation and flexible memory protection as defined by the architecture. The mapping mechanism consists of software-managed TLBs that support variable-sized pages with per-page properties and permissions.
- The integrated 512-Kbyte L2 cache is organized as 2048 eight-way sets of 32-byte cache lines based on 36-bit physical addresses The SRAM can be configured with memory-mapped registers as externally accessible memory-mapped SRAM in addition to or instead of cache.
- The fully programmable DDR SDRAM controller supports most JEDEC standard x8, x16, or x32 DDR and DDR2 memories available. In addition, unbuffered and registered DIMMs are supported. mixing different memory types or unbuffered and registered DIMMs in the same system is not supported. Built-in error checking and correction (ECC) ensures very low bit-error rates for reliable high-frequency operation. Dynamic power management and auto-precharge modes simplify memory system design. A large set of special features, including ECC error injection, support rapid system debug.
- The PIC prioritizes and manages interrupts directed to the int signal. It also manages the interrupts generated by the PIC itself and by off-chip interrupt sources. The PIC is compliant with the OpenPIC architecture. The interrupt controller provides interrupt management, and is responsible for receiving hardware-generated interrupts from different sources, prioritizing them, and delivering them to the CPU for servicing. The PIC receives interrupt signals from three sources: external to the integrated device, internal to the integrated device, and intrinsic to the PIC itself.
- The two-wire I2C bus minimizes interconnections between devices. The synchronous, multiple-master I2C bus allows the connection of additional devices to the bus for expansion and system development. The bus includes collision detection and arbitration that prevent data corruption if two or more masters attempt to control the bus simultaneously.
- The DUART consists of two universal asynchronous receiver/transmitters (UARTs). The UARTs act independently; all references to UART refer to one of these receiver/transmitters. Each UART is clocked by the core complex bus (CCB) clock. The DUART programming model is compatible with the PC16552D. The UART interface is point to point, meaning that only two UART devices are attached to the connecting signals.
- The PCI Express controller provides the mechanism to communicate with PCI Express devices. The PCI Express controller connects the internal platform to a 2.5-GHz serial interface. MPC8548E offers up to a x8 interface link. As both an initiator and a target device, the PCI Express interface is capable of high-bandwidth data transfer and is designed to support next generation I/O devices. Upon coming out of reset, the PCI Express interface performs link width negotiation and exchanges flow control credits with its link partner. Once link auto negotiation is successful, the controller is in operation.
- A block diagram of the integrated security engine’s internal architecture is shown here. The SEC is a modular and scalable security core optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. it is not a protocol processor, the SEC is designed to perform multi-algorithmic operations in a single pass of the data, The bus interface module is designed to transfer 64-bit words between the internal bus and any register inside the SEC.
- The MPC8548E serial RapidIO controller consists of a RapidIO endpoint and the RapidIO messaging unit (RMU). The serial RapidIO interface provides a RapidIO port and message unit to communicate with other RapidIO devices. RapidIO endpoint supports Nine outbound ATMU windows with each window having up to 32 sub windows except the default Window, Five inbound ATMU windows, Logical outbound packet time-to-live counter to prevent local processor from hanging when the RIO interface fails.
- The PCI/X controller acts as a bridge between the PCI/X interface and the OCeaN switch fabric. The PCI/X controller connects the OCeaN to the PCI bus, to which I/O components are connected. The PCI bus uses a 32- or 64-bit multiplexed address/data bus, plus various control and error signals. The PCI/X interface supports address and data parity with error checking and reporting. The integrated processor’s PCI/X interface functions both as a master (initiator) and a target device.
- The DMA controller has four high-speed DMA channels. Both the e500 core and external devices can initiate DMA transfers. All channels are capable of complex data movement and advanced transaction chaining. Operations such as descriptor fetches and block transfers are initiated by each channel. A channel is selected by the arbitration logic and information is passed to the source and destination control blocks for processing. The source and destination blocks generate read and write requests to the address tenure engine, which manages the DMA master port address interface.
- The enhanced three-speed Ethernet controllers (eTSECs) of the device interface to 10 Mbps, 100 Mbps, and 1 Gbps Ethernet/IEEE 802.3 networks and devices featuring generic 8-16-bit FIFO ports. For Ethernet, an external PHY or SerDes device is required to complete the interface to the media. Each eTSEC supports multiple standard media-independent interfaces, of which the FIFO interface bypasses the Ethernet MAC. Four eTSECs are available, providing flexible options for connectivity and control access at different speeds.
- The MPC8548E is a very flexible device and can be configured to meet many system application needs. In order to build a system, many factors should be considered. The MPC8548E can be used for control processing in applications such as routers, switches, internet access devices, firewall and other packet filtering processors, network attached storage, storage area networks, imaging, and general-purpose embedded computing. Here illustrates is the MPC8548E in a virtual private network (VPN) access router that is enabled through PCI Express and Ethernet. It shows the MPC8548E in a redundant array of independent disks (RAID) controller application.
- Thank you for taking the time to view this presentation on “ MPC854X” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Freescale Semiconductor site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility. You may visit Element 14 e-community to post your questions.