Esencia Company Overview and Design Services Capabilities Founders: Ravi Satrawada, Alpesh Oza, Miguel Guerrero

1. © 2014 Esencia Technologies, Inc.
Esencia Technologies, Inc.
Your trusted design partner, from concept to product

2. © 2014 Esencia Technologies, Inc.
Company Overview
Facts
 Located in Silicon Valley
 Incorporated in 2006
 Privately held
 Self-funded, cash flow positive
Team
 50 Employees
 450+ person-years of Experience
 25+ Successful ASIC and FPGA Products
 10+ Software Projects
 Cost effective/ secure EDC Design model for Long term projects
 Team holds 68 patents with another 19 pending
 Esencia holds 3 patents in EScala Design Platform
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3. © 2014 Esencia Technologies, Inc.
Our Core Business
Services
 Turnkey Design
 Software / Firmware / Driver Development
 ASIC / FPGA Frontend & Backend Design
 Consulting Services
 Offshore Extended Design Center (EDC)
IP Cores & Design Platform
 Soft IPs in areas of Security, Networking, Video & DSP
 EScala – Configurable CPU Design Platform
 Customization & Integration of IP’s
 Custom IP development
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4. © 2014 Esencia Technologies, Inc.
Domain Expertise
Proven track-record
 Software / firmware /driver Development
 CPU Architecture
 Custom Digital Signal Processing
 Video / Signal processing / SoC Architecture
 Networking
 High speed interfaces, PCIe, USB, SATA, DDR
 NVM applications
 Deep Expertise in Low Power SoC design flow
Differentiated IP portfolio
 Encryption cores
 Configurable FFT core, Viterbi, Reed Solomon Codec, Turbo & LPDC
 EScala: Configurable CPU Design Platform
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5. © 2014 Esencia Technologies, Inc.
Founders & the team
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Ravi Satrawada, CEO
• DSP/ Wireless System
Architechture
• LTE, GPS , WiFi, bluetooth,
WiMax, MoCA, Satellite
communications
• Encryption Algorithms
• Previous: RFMD, ComTier,
Stanford Telecom
• Masters in Telecommunication from
IIT Kharagpur
Alpesh Oza, COO
• SOC Architecture
• ASIC Methodology & Program
Management
• High-speed Interfaces
• DDR, PCIe, SATA, USB3
• EScala Design Platform
• Previous: Intel
• Masters from CSU-Sacramento
Miguel Guerrero, CTO
• Firmware / Architecture
• Video / Signal Processing
• 3D, Gesture, Augmented Reality
• Android / Embedded linux
• Escala compiler and user interface
• Previous: Intel, NVIDIA
• MSEE from Universidad Politecnica
de Valencia
20+
years
20%
16 - 20
years
24%
11 - 15
years
30%
6 - 10
years
18%
2 - 5
years
8%
Experience
Ph.D
6%
Masters
60%
Bachelors
34%
Educational
Qualifications Architecture
14%
Sofware
22%
ASIC/FPGA
Design
20%
Asic/FPGA
Verification
24%
Physical
Design &
DFT
16%
Admin/
Support
4%
Expertise

6. © 2014 Esencia Technologies, Inc.
Customer Success Stories
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7. © 2014 Esencia Technologies, Inc.
Projects Portfolio - Software/ Drivers/ Firmware
Mobile imaging subsystem
 Driver Design / modification
System Simulator / Modeling
 Development of a multi-CPU instruction set simulator
Platform porting
 Conversion and generation to different CPU platforms
GPU acceleration
 Application acceleration, performance enhancement
Development Platform specific Apps
 Knowledge base in Linux, Android, iOS, embedded OS
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8. © 2014 Esencia Technologies, Inc.
Projects Portfolio - Video & Image processing
3D Vision & Image Sensor computing
 Architecture, RTL & Integration, Verification, FPGA, P&R
Video analytics accelerator for x86 Processor
 Architecture, RTL, Verification, FPGA & Palladium prototyping, Silicon
bring-up & Validation, Customer support
2nd Generation Video analytics accelerator for x86 Processor
 Algorithm to HW-Architecture definition, Performance study & Modeling,
Benchmark against GPU solutions, Integration of dual Atom CPU
system, RTL development
IR Image Signal Processor
 Chip Target specification turn-key, Process & IP selection
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9. © 2014 Esencia Technologies, Inc.
Projects Portfolio – SOC Development
Game Platform Memory Subsystem
 HW-Architectural Proposal and Micro Architecture
Set-top Box SoC
 Architecture and design of memory sub-system design, Multi-core
Programmable Display processing pipeline architecture, FRC Algorithm
Mapping and FW development, Video data compression for memory
bandwidth reduction
SERDES
 Micro-Architecture, RTL implementation and Verification, Multi Voltage
domain Power Management controller
CPU architecture expertise
 ARM / x86 integration and custom DSP design
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10. © 2014 Esencia Technologies, Inc.
Projects Portfolio – Wireless/ Networking
Game Platform Memory Subsystem
 HW-Architectural Proposal and Micro Architecture
LTE baseband
 System Performance Validation, System Modeling, HW architecture
Ultra Low power customized IEEE802.11b/g baseband
 IP provider, IP integration, Architecture, Low power optimization, RTL
implementation, Verification Flow, FPGA support
Bluetooth baseband
 Architecture of baseband subsystem, RTL design and Verification,
Support of FPGA prototyping
Networking
 High speed Switch / Routers
 High speed Lookup engines
 Low Latency Networking i.e. High frequency trading(HFT)
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11. © 2014 Esencia Technologies, Inc.
Design Type
Technology
Node (nm)
Size
(mm2)
Performance
(MHz)
PCIe, SATA, USB3 22 nm 10 x 3 4000 (800 GHz)
HDMI, USB2, SDIO, MIPI 14 nm 3 x 4 800
Other Interfaces 14 nm 3 x 4 800
3D Image Processor Gen IV 40 LP TSMC 4x4 333
3D Image Processor Gen V 40 LP TSMC 7x7 333
Video Co Processor
65 TSMC with
eDRAM
8 x 8 500
DDR Memory Controller Soft IP 65 TSMC 3 x 3 1600
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Projects Portfolio
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12. © 2014 Esencia Technologies, Inc.
IP Cores available from Esencia
• EScala DSP Design Platform programmable accelerator:
 Design Time Reduction(c-source code design entry)
 Risk Reduction (re-programmability)
• Security Cores: AES, SHA-1/MD5, RSA
• Communication-Cores
 Fully configurable FFT cores
 Turbo Decoder
 Viterbi Decoder
 Reed Solomon Codec
 Matlab/ RTL-DSP component library
• Video Cores
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13. © 2014 Esencia Technologies, Inc.
Thank You
Esencia Technologies, Inc.
March 2014