1. VLSI email id:vlsi@pantechmail.com
SI.No Topics Field
PSVLS 1 Real Time Hardware Co-simulation of Edge Detection for Video Processing System
System Generator & Signal
PSVLS 2 BPSK System on Spartan 3E FPGA
Processing
IEEE 2012
PSVLS 3 Implementation of PSK and QAM demodulators on FPGA
PSVLS 4 Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation
PSVLS 5 Platform-Independent Customizable UART Soft-Core
PSVLS 6 VLSI Architecture of Arithmetic Coder Used in SPIHT
PSVLS 7 Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
PSVLS 8 Single Phase Clocked Quasi Static Adiabatic Tree Adder
PSVLS 9 Enhanced Power Gating Schemes for Low Leakage Low Ground Bounce Noise in Deep
Low Power Design
Submicron Circuits
IEEE 2012
PSVLS 10 Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
PSVLS 11 Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution
Networks
PSVLS 12 Design of Low Voltage Low Power Operational Amplifier
PSVLS 13 Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS
Circuits
PSVLS 14 A Novel Architecture for VLSI Implementation of RSA Cryptosystem
PSVLS 15 FPGA Hardware of the LSB Steganography Method
Communication
Cryptography &
IEEE 2012
PSVLS 16 A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL
PSVLS 17 An efficient FPGA implementation of the Advanced Encryption Standard algorithm
PSVLS 18 A Novel Data Embedding Method Using Adaptive Pixel Pair Matching
PSVLS 19 VHDL Implementation of a Flexible and Synthesizable FFT Processor
PSVLS 20 An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion
PSVLS 21 Medical Image Fusion Based on Redundancy DWT and Mamdani Type Min-sum Mean-of-
Soft Core Processor Design
max Techniques with Quantitative Analysis
PSVLS 22 Edge Detection of Angiogram Images Using the Classical Image Processing Techniques
IEEE 2012
PSVLS 23 Input/Output Peripheral Devices Control through Serial Communication using Microblaze
Processor
PSVLS 24 Variable Scaling Factor based Invisible Image Watermarking using Hybrid DWT – SVD
Compression - Decompression Technique
PSVLS 25 A Level Set Based Deformable Model for Segmenting Tumors in Medical Images
PSVLS 26 Adaptive Steganalysis of Least Significant Bit Replacement in Grayscale Natural Images
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2. VLSI email id:vlsi@pantechmail.com
PSVLS 27 Analysis of CT and MRI Image Fusion using Wavelet Transform
PSVLS 28 Design of Modified Low Power Booth Multiplier
PSVLS 29 An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
PSVLS 30 Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time
Mobile Video Applications Applications
Soft Core Processor Design
PSVLS 31 Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA
A Novel Architecture for an Efficient Implementation of Image Compression Using 2D-DWT
IEEE 2012
PSVLS 32
PSVLS 33 Background Subtraction Algorithm for Moving Object Detection in FPGA
PSVLS 34 Design and Implementation of the Discrete Wavelet Transform on an FPGA Platform to
Process Data Sets of up to Three Dimensions
PSVLS 35 Gesture Recognition Using Field Programmable Gate Arrays
PSVLS 36 Median Filter on FPGAs
PSVLS 37 An Autoadaptive Edge-Detection Algorithm for Flame and Fire Image Processing
PSVLS 38 An Efficient Denoising Architecture for Removal of Impulse Noise in Images
PSVLS 39 Real Time Smart Car Lock Security System Using Face Detection and Recognition
PSVLS 40 A Novel Non-payment Vehicle Searching Method for Multilane-Free-Flow Electronic-Toll-
Collection Systems
(ecurity & System Generator
PSVLS 41 Implementation of a Home Automation System through a Central FPGA Controller
PSVLS 42 Design of Intelligent Home Appliance Control System Based on FPGA and ZIGBEE
IEEE 2012
PSVLS 43 New Clock Generation Techniques for Synchronous Sampling of 16-QAM RF Signals
PSVLS 44 QPSK Modulator on FPGA
PSVLS 45 Implementation of a QPSK System on FPGA
PSVLS 46 Models Simulation based on HDL-Simulink Platform
PSVLS 47 Simulation and Implementation of a BPSK Modulator on FPGA
PSVLS 48 An improved three-factor authentication scheme using smart card with biometric privacy
protection
Wireless Communication
PSVLS 49 The Ship Monitoring and Control Network System Design
IEEE 2011
PSVLS 50 Autonomous Navigation for an Unmanned Mobile Robot in Urban Areas
PSVLS 51 A Generic Framework for Three-Factor Authentication: Preserving Security and Privacy in
Distributed Systems
PSVLS 52 A Low-Cost GPS&INS Integrated System Based on a FPGA Platform
PSVLS 53 An embedded high sensitivity navigation receiver for GPS
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3. VLSI email id:vlsi@pantechmail.com
PSVLS 54 Hardware Efficiency Comparison of AES Implementations
PSVLS 55 Efficient Design and Implementation of FFT
PSVLS 56 Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting
PSVLS 57 Design of Sequential Elements for Low Power Clocking System
PSVLS 58 Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design
PSVLS 59 Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS
Circuits
PSVLS 60 Parameterized FPGA-Based Architecture For Parallel 1-D Filtering Algorithms
Low Power Design
PSVLS 61 A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors
IEEE 2011
PSVLS 62 Low Power Single Bitline 6T SRAM Cell With High Read Stability
PSVLS 63 Low Power Subthreshold D Flip Flop
PSVLS 64 Low Leakage Power SRAM Cell for Embedded Memory
PSVLS 65 A Novel Low-Leakage 8T Differential SRAM Cell
PSVLS 66 Adiabatic Technique for Energy Efficient Logic Circuits Design
PSVLS 67 A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM
Design
PSVLS 68 Performance Analysis of Power Gating designs in Low Power VLSI Circuits
PSVLS 69 Low-Power and Area-Efficient Carry Select Adder
PSVLS 70 Operation Improvement of Indoor Robot by Gesture Recognition
Security Based
PSVLS 71 Improving ATM Security Via Face Recognition
IEEE 2011
PSVLS 72 Design of Vehicle Positioning System Based on FPGA
PSVLS 73 A Novel Area-Throughput Optimized Architecture for the AES Algorithm
PSVLS 74 Thwarting Control-Channel Jamming Attacks from Inside Jammers
PSVLS 75 Image Processing in Dynamic Reconfigurable Platform
PSVLS 76 Real-Time Object Tracking System on FPGAs
Image Processing
PSVLS 77 Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT
IEEE 2011
PSVLS 78 A Universal Background Subtraction Algorithm for Video Sequences
PSVLS 79 A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform
PSVLS 80 Power Efficient Motion Estimation Algorithm and Architecture Based on Pixel Truncation
PSVLS 81 Architectural Implementation of High Speed Optical Flow Computation Based on Lucas-
Kanade Algorithm
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4. VLSI email id:vlsi@pantechmail.com
PSVLS 82 Discrete Wavelet Transform-Based Satellite Image Resolution Enhancement
PSVLS 83 An Efficient Denoising Architecture for Removal of Impulse Noise in Images
PSVLS 84 Dynamic Hand Gesture Recognition for Human- Computer Interactions
Dynamic Power Estimation for Motion Estimation Hardware
Image Processing
PSVLS 85
IEEE 2011
PSVLS 86 Realization of a LSB Information Hiding algorithm Based on Lifting Wavelet Transform
Image
PSVLS 87 Blind Image Watermarking Using a Sample Projection Approach
PSVLS 88 A Novel Power Reduction Technique for Block Matching Motion Estimation Hardware
PSVLS 89 An improved method of image edge detection based on wavelet transform
PSVLS 90 Mathematical Morphological Edge Detection For Remote Sensing Images
PSVLS 91 A New Adaptive Weight Algorithm for Salt and Pepper Noise Removal
PSVLS 92 FPGA Implementation of AES Algorithm
Wireless Jamming Attacks under Dynamic Traffic Uncertainty
Wireless communication
PSVLS 93
PSVLS 94 Car Monitoring, Alerting and Tracking Model
IEEE 2010
PSVLS 95 FPGA-Based GPS Application System Design
PSVLS 96 An Embedded System and RFID Solution For Transport Related Issues
PSVLS 97 Keyless Car Entry through Face Recognition Using FPGA
PSVLS 98 Design of AM Modulation Signal Generator Based on Matlab/DSP Builder
PSVLS 99 Ground Bounce Noise Reduction of Low leakage 1-bit Nano-CMOS based Full Adder Cells
for Mobile Applications
PSVLS 100 CMOS Full-Adders for Energy-Efficient Arithmetic Applications
PSVLS 101 Variability Resilient Low-power 7T-SRAM Design for nano-Scaled Technologies
PSVLS 102 A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS Technology Power Analysis
PSVLS 103 Dual Stack Method: A Novel Approach to Low Leakage and Speed Power Product VLSI
IEEE 2010
Design
PSVLS 104 Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
PSVLS 105 Optimal Design For Ground Bounce Noise Reduction Using Sleep Transistor
PSVLS 106 A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip–Flops With
Embedded Logic
PSVLS 107 Design of A Low Power Flip-Flop Using CMOS Deep Submicron Technology
PSVLS 108 A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT
Variations on Nanoscale VLSI Systems
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5. VLSI email id:vlsi@pantechmail.com
PSVLS 109 Optimization of Processor Architecture for Image Edge Detection Filter
PSVLS 110 Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster
Number
PSVLS 111 Message Encoding in Images Using Lifting Schemes
PSVLS 112 Medical Image Retrieval using Energy Efficient Wavelet Transform
PSVLS 113 A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet
Transform
PSVLS 114 Design of Pipelined FFT Processor Based on FPGA
PSVLS 115 An FPGA-based Architecture for Linear and Morphological Image Filtering
Image Processing
IEEE 2010
PSVLS 116 Motion human detection based on background subtraction
PSVLS 117 GPS-GSM Integration for Enhancing Public Transportation Management Services
PSVLS 118 A Color Image Segmentation algorithm Based on Region Growing
PSVLS 119 Reconfigurable Hardware for Median Filtering for Image Processing Applications
PSVLS 120 Adaptive 2-D Wavelet Transform Based on the Lifting Scheme with Preserved Vanishing
Moments
PSVLS 121 Performance Evaluation of DES and Blowfish Algorithms
PSVLS 122 A new and efficient algorithm for the removal of high density salt and pepper noise in
images and videos
PSVLS 123 Ocean Wave Observation by GPS Signal
PSVLS 124 Performance Comparison and Analysis of PSK and QAM
18
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