1. Upgrading to SystemVerilog for
FPGA Designs
- Presented at FPGA Camp Bangalore
Camp,
Srinivasan Venkataramanan
Chief Technology Officer
CVC Pvt. Ltd.
www.cvcblr.com

2. Agenda
 Introduction to SystemVerilog (SV)
 SV - RTL Design constructs
 SV Interface
 SV Assertions
 Success Stories
 SV-FPGA Ecosystem
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3. About the presenter
Srinivasan Venkataramanan, CTO, www.cvcblr.com
 http://www.linkedin.com/in/svenka3
 Over 13 years of experience in VLSI Design & Verification
 Designed, verified and lead several multi-million ASICs in
image processing, networking and communication domain
 Worked at Philips, Intel, Synopsys in various
p , , y p y
capacities.
 Co-authored leading books in the Verification domain.
 Presented papers, tutorials in various conferences,
publications and avenues.
bli ti d
 Conducted workshops and trainings on PSL, SVA, SV,
VMM, E, ABV, CDV and OOP for Verification
 Holds M Tech in VLSI Design from prestigious IIT, Delhi.
M.Tech f om p estigio s IIT Delhi
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4. What is SystemVerilog?
 Superset of Verilog-2001
 IEEE 1800-2005 standard
 More information @ www.SystemVerilog.org
M i f ti S t V il
 Several books available:
 SystemVerilog Assertions Handbook – Ajeetha, Ben Cohen,
y g j , ,
Srinivasan, www.systemverilog.us
 A Pragmatic approach to VMM adoption – Ajeetha, Ben,
Srinivasan
 SystemVerilog for Designers, Stuart Sutherland
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5. SystemVerilog - Evolution
Classes,
Temporal Sequential
inheritance,
Property Regular
Definitions Expressions OOP based
polymorphism Testbench
Properties – capture temporal Constraint driven Constrained
randomization
Behavior: Assertion,
B h i A ti Functional Coverage
Semaphores Random Data
Assumption, Coverage Inheritance
Mailboxes Generation
SVA Polymorphism
Queues,
MDAs
MDA Data structures VirtualtiInterface g p,
Associative
A i
Covergroup,
sampling
enums & Dynamic
arrays
Strings Enhanced programming Verilog 2001
(do while, break continue,
hile break, contin e
++, --, +=. Etc.)
DPI – Quickly connect C/C++
Enhanced Design
Coverage &
Very efficient and ease of use
Better logical blocks – Constructs, modeling
Assertion API
always_comb, ff latch
always comb _ff, _latch SV-Design
SV D i
DPI interface
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6. SystemVerilog - User view
Has 5 major parts:
SVD – SystemVerilog for Design
SVA – SystemVerilog Assertions
SVTB – SystemVerilog Testbench
SV-DPI – Direct Programming Interface
for better C/C++ interface
SV-API – Application Procedural Interface
 for Coverage, Assertion etc
Coverage etc.
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7. Reference Books
Source A Pragmatic Approach to VMM Adoption 2006
for Tutorial ISBN 0-9705394-9-5, http://www.systemverilog.us
and Code
nd
(7)
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8. SV Design-Data Types
 Enhanced data types:
 2-state (bit) logic
2 state ),
 Potential memory & run time
improvement (2-state)
 High level models can avail 2-state
 Clearer descriptions: a Verilog reg is
NOT necessarily a “register”
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9. SV Design – Data types
 User Defined types
 Enums – local typedef
local,
 Strict type checking, typecast
 Better modeling style easy to read
style, read,
maintain
 State
St t encoding - via language (not via
di i l ( t i
tool scripts)
 Ease of debug, waveform
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10. SV Design – logic modeling
 Verilog RTL – only always block
 Combinatorial & Sequential
 Inference by sensitivity list
 One of the top 10 error prone usages – more for
newbie
 SV: Enhanced Modeling
 always_comb
y _
 always_ff
 always_latch
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11. What logic is being modeled?
 Modeling
combinatorial logic?
 Use always_comb
y
 Modeling Sequential
g q
logic?
 Use always_ff
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12. What logic is being modeled?
 Modeling Latch?
 Use always_latch
 Reduces Synthesis-
Simulation discrepancies
 Language captures design
intent (not pragmas, tool
settings)
g )
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13. Abstract modeling - struct
 C-like struct
lk
 Well proven
data structure
abstraction
technique
 Cut down
do
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15. Interfaces – bread-n-butter of modern
bread n butter
SoCs
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16. Interfaces – SPI, OCP
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17. Old fashioned hook-up–
Verilog description
 Too verbose
 Highly error
prone
 Maintenance
head-ache
 Not easy to
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reuse
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18. Typical sub-systemusing Verilog
Modeled
AHB AHB
Master1 Master2
AHB AHB
Slave1 Slave2
 SoC is built using IPs – lot of ReUse
 I di id
Individual blocks pre-verified in standalone
l bl k ifi d i t d l
 Most Bugs Occur Between Blocks
 A good number of “Wiring” Errors
d b f “Wi i ” E
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19. Hookup various blocks – the old way
addr module top();
top mem_controller mc (clk, rst_n, dout,
addr, din, wr_rd);
Mem
din memory mem0(clk,rst n, addr, din,
mem0(clk,rst_n,
m_Controller
wr_rd, dout);
wr_rd Memory endmodule
module mem_controller (
dout
d t input clk, rst_n,[7:0] dout,
output [3:0] addr, [7:0] din,
wr_rd);
module memory(output [7:0] dout,
dout task write();
();
input clk, rst_n, [3:0] addr, addr <= ‘haa;
[7:0] din, wr_rd); din <= $random;
always @(posedge clk) wr_rd = 1’b1;
if (wr rd)
(wr_rd) @(p
@(posedge clk);
g );
mem[addr] <= din; wr_rd = 1’b0;
endmodule : memory endtask : write
CVC Copyright Protectedendmodule
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20. Interface
interface simple_bus; // Define the interface module cpuMod(simple_bus b, input bit
logic req, gnt; clk);
...
logic [7:0] dd d
l i [ ] addr, data;
endmodule
logic [1:0] mode;
logic start, rdy;
p _
endinterface: simple_bus module top;
logic clk = 0;
simple_bus sb_intf; // Instantiate the
module memMod(simple_bus a, // Use the interface
simple_bus interface memMod mem(sb_intf, clk);
input bit clk); cpuMod cpu(.b(sb_intf), .clk(clk));
cpu( b(sb intf) clk(clk));
logic avail; endmodule
// a.req is the req signal in the ’simple_bus’
interface
always @(posedge clk) a.gnt <= a.req &
a gnt a req
avail;
endmodule CVC Copyright 2008
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21. Assertion-Based Verification
 It’s a verification technique
 Instruments requirements with assertions
 Clarifies eq i ements ith e ec table lang age
Cla ifies requirements with executable language
 Enables tools to preview assertion waveforms
 Instruments design with assertions
 Added visibility
 White-box testing into its internal state
 Provision for functional coverage information
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22. Applying ABV - Bus based SoC
Simulate
 What happened du g sim?
at appe ed during s
 Any protocol violation?
 How many RW?
 Was xfer interrupted?
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23. Use assertions sparingly
 Non-intrusive
 Works with any existing flow
 The more you add, the more you gain
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24. Ross Video – SV verification
for FPGAs
 The Ross Video team created a robust verification
environment utilizing the VMM's built-in:
 self-checking
lf h ki
 scenario generation
 transaction-level channels
 transactors and
 messaging services.
 Extensive use of SystemVerilog assertions (SVA)
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25. Advantages of interface
g
customer success stories
 Better design style
 Disambiguate the communication
g
 Forces to have a clear interface
specification upfront – takes little more
time, b saves much more later on
but h l
 Reduces integration time
 Add Assertions to interface, every block
using it shall have to comply with the
protocol
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26. Impact of Interface
module netproc (SX_ux_soc, SX_ux_en, SX_ux_data, SX_ux_clav,
interface utopia_i; SX_ux_clk, SX_cpu_BusMode, SX_cpu_Addr, SX_cpu_Sel,
wire soc; // start of cell SX_cpu_Data, SX_cpu_Rd_DS, SX
SX D t SX Rd DS SX_cpu_Wr_RW,
W RW
wire en; // enable SX_cpu_Rdy_Dtack, rst, clk);
inout SX_ux_soc;
Syste
wire [7:0] data; // data
wire clav; // cell available inout SX_ux_en;
wire clk; // ATM layer clock inout [7:0] SX_ux_data;
endinterface inout SX_ux_clav;
Verilog9
V
inout SX ux clk;
SX_ux_clk;
emVerilog
interface cpu_i(input bit rst); inout SX_cpu_BusMode;
wire BusMode; inout [11:0] SX_cpu_Addr;
logic [11:0] Addr; inout SX_cpu_Sel;
logic Sel; inout [7:0] SX_cpu_Data;
wire [ 7:0] Data; inout SX_cpu_Rd_DS;
logic
g Rd_DS; ; inout SX_cpu_Wr_RW;
95
logic Wr_RW; inout SX_cpu_Rdy_Dtack;
wire Rdy_Dtack; input rst;
endinterface input clk;
wire SX_ux_soc;
module netproc(utopia_i ux, cpu_i cpu, wire SX_ux_en;
input bit clk); wire [7:0] SX_ux_data;
endmodule
d d l wire SX ux clav;
SX_ux_clav;
wire SX_ux_clk;
wire SX_cpu_BusMode;
wire [11:0] SX_cpu_Addr;
wire SX_cpu_Sel;
wire [7:0] SX_cpu_Data;
- 3X more co pact
3 o e compact wire SX_cpu_Rd_DS;
_ p _ _
wire SX_cpu_Wr_RW;
- Fewer wiring mistakes wire SX_cpu_Rdy_Dtack;
wire rst;
wire clk;
endmodule 26

27. Ecosystem around SV-FPGA
 All major EDA vendors support SV for
Design (simulators)
g ( )
 Synthesis: Synplify, leonardo
 FPGA vendors – need more support
 Latest update pending
 Books, tutorials – plenty:
 www.aldec.com/Downloads
 Trainings: www cvcblr com/trainings
www.cvcblr.com/trainings
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28. Aldec’s Active-HDL
Design-flow manager
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29. SV & FPGA tool support
 Active-HDL
 SV-Design, Assertions (SVA + PSL)
 Interface,
Interface Debug
 Modelsim-DE
 SV-Design, SVA, PSL
 Synplify
 SV-Design, synthesizable constructs
 Leonardo
 Details awaited, call Mentor
 Xilinx, Altera
 Unknown, call your vendor
, y
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30. SV & FPGA advanced
technologies
 With adoption of SV, modern design
p
paradigms emerge
g g
 ASIC prototyping – EVE Design systems
 Jasper s
Jasper’s ActiveDesign is one such
technology
 Can create waveforms for AHB, AXI etc.
right from RTL
 No TB required, plain RTL + ActiveDesign
q ,p g
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31. Jasper’s ActiveDesign
 Capture “information” during RTL design
p
phase:
 Designer makes an assumption about the
latency of output, FIFO size etc.
y p ,
 “show me a proof/witness/waveform” for such
an occurrence
 Can we optimize the latency to say 5
 What-if I change the FIFO size to 32 here etc.
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32. CVC Trainings –
www.cvcblr.com/trainings
 Verification Centric Course
 Comprehensive Functional Verification (CFV)
 Language Course
 IEEE 1800 SystemVerilog for Design (SVD)
 IEEE 1800 SystemVerilog Assertions (SVA)
 IEEE 1800 SystemVerilog for Verification (SVTB)
 IEEE 1850 Property Specification Language (PSL)
 IEEE 1647 E
1647,
 Methodology
 VMM, OVM, AVM, CDV, ABV
 Workshops
 Gate Level Si l ti (GLS)
G t L l Simulation
 ABV Beyond RTL (ABV)
 Coverage Driven Verification (CDV)
 OOP for functional Verification
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33. CVC Publications, tutorials, workshops
•Quick start guides Tutorials
guides,
• SVA
• PSL
• VMM
•Workshops :
•Gate Level Simulation
•ABV beyond RTL
y
•Coverage Driven Verification
•OOP for Verification
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