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CFD and FPGAs

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Ongoing developments of FPGAs and PCIe technologies - CFD acceleration - Gabriel Caffarena Laboratory of Integrated Systems (LSI) Universidad Politécnica de Madrid CFD on Future Architectures C 2 A 2 S 2 E – DLR Braunschweig October 2009
Agenda ,[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Agenda ,[object Object],[object Object],[object Object],[object Object]
CFD with FPGAs ,[object Object],[object Object]
CFD with FPGAs ,[object Object],[object Object],[object Object],PC HOST
CFD with FPGAs FPGAs ,[object Object],[object Object],[object Object]
CFD with FPGAs Design flow ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],CFD
CFD with FPGAs ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],FPGA
Agenda ,[object Object],[object Object],[object Object],[object Object]
Hardware design methodology ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Hardware design methodology ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Hardware Design Methodology Precision Analysis ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Hardware Design Methodology Precision Analysis Sensibility Analysis Error=f(parameters, bits) Fast WL Optimization CFD code Accuracy Check Double-precision vs Fixed-point Error parameters
Hardware Design Methodology C to VHDL ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],if (z!=b-c) z=(a+b)*c;
Hardware Design Methodology FPGA flow: bitstream generation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Agenda ,[object Object],[object Object],[object Object],[object Object]
Current results ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Current results Procedural approach Speedup x1.6 (Theoretical limit x2.8: Amdahl’s law ) Precision 10 -5 PCIe bottleneck (16 Gbps  6-8 Gbps)
Current results Algorithmic approach ,[object Object],[object Object],[object Object],[object Object],[object Object],FPGA [rho, u, p] in RAM [rho, u, p] t [rho, u, p] out PCI-e PCI-e RAM DMA CPU Euler 1D DDR FIFOs
Current results Lessons learnt ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],New FPGA boards DINI - XILINX GIDEL - ALTERA
Agenda ,[object Object],[object Object],[object Object],[object Object]
Future work ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Future work ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Future work ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Projects and collaborations ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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CFD and FPGAs

  • 1. Ongoing developments of FPGAs and PCIe technologies - CFD acceleration - Gabriel Caffarena Laboratory of Integrated Systems (LSI) Universidad Politécnica de Madrid CFD on Future Architectures C 2 A 2 S 2 E – DLR Braunschweig October 2009
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  • 14. Hardware Design Methodology Precision Analysis Sensibility Analysis Error=f(parameters, bits) Fast WL Optimization CFD code Accuracy Check Double-precision vs Fixed-point Error parameters
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  • 19. Current results Procedural approach Speedup x1.6 (Theoretical limit x2.8: Amdahl’s law ) Precision 10 -5 PCIe bottleneck (16 Gbps  6-8 Gbps)
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