1. SIMULATION AND IMPLEMENTATION OF LOGIC GATES
AIM:
To simulate and implement the logic gates using XC3S400 FPGA kit
APPARATUS REQUIRED
1. PC with XILINX ISE 9.1i
2. XC3S400 FPGA kit
PROGRAM
module logicgates(a,b,y1,y2,y3,y4,y5,y6,y7,y8);
input a,b;
output y1,y2,y3,4y,y5,y6,y7,y8;
buf (y1,a);
not (y2, b);
or (y3,a,b);
and (y5,a,b);
nand (y6,a,b);
xor (y7,a,b);
xnor (y8,a,b);
end module
RESULT:
Thus the logic gates have been simulated and implemented using XC3S400 FPGA kit.

2. SIMULATION AND IMPLEMENTATION OF HALF ADDER AND FULL ADDER
AIM:
To simulate and implement half adder and full adder using XC3S400 FPGA kit
APPARATUS REQUIRED:
1. PC with XILINX ISE 9.1 i
2. XC3S400 FPGA kit
PROGRAM:
HALF ADDER:
module halfadder (a,b,sum,carry);
input a,b;
xor (sum,a,b);
and (carry,a,b);
end module
FULL ADDER:
module fulladder (a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
end module
RESULT:
Thus the half adder and the full adder were simulated and implemented using XC3S400
FPGA kit.

3. SIMULATION AND IMPLEMENTATION OF HALF SUBTRACTOR AND FULL
SUBTRACTOR
AIM:
To simulate and implement half subtractor and full subtractor using XC3S400 FPGA kit.
APPARATUS REQUIRED:
1. PC with XILINX ISE 9.1 i
2. XC3S400 FPGA kit
PROGRAM:
HALF SUBTRACTOR
module halfsubtractor (x,y,difference,borrow);
input x,y;
output difference, borrow;
assign difference = (x^y);
assign borrow = (~x&y);
end module

4. FULL SUBTRACTOR
module fulsubtractor (x,y,bin,d,bout);
input x,y,bin;
output d,bout;
assign d = x^y^bin;
assign bout = (~x&y)|(~x&bin)|(y&bin);
end module
RESULT:
Thus the half subtractor and full subtractor were implemented using XC3S400 FPGA kit.
SIMULATION AND IMPLEMENTATION OF PARALLEL ADDER

5. AIM:
To simulate and implement parallel adder using XC3S400 FPGA kit.
APPARATUS REQUIRED:
1. PC with XILINX ISE 9.1 i
2. XC3S400 FPGA kit
PROGRAM:
module paralleladder (a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output [3:0] sum;
assign {cout,sum} = a+b+Cin;
end module
RESULT:
Thus the parallel adder was simulated and implemented using XC3S400 FPGA kit.
SIMULATION AND IMPLEMENTATION OF PARALLEL SUBTRACTOR

6. AIM:
To simulate and implement parallel subtractor using XC3S400 FPGA kit.
APPARATUS REQUIRED:
1. PC with XILINX ISE 9.1 i
2. XC3S400 FPGA kit
PROGRAM:
module parallelsubtractor (x,y,bin,difference,bout);
input [3:0] x,y;
input bin;
output bout;
assign {bout,difference} = x-y-bin;
end module
RESULT:
Thus the parallel subtractor was simulated and implemented using XC3S400 FPGA kit.
SIMULATION AND IMPLEMENTATION OF CARRY LOOK-AHEAD ADDER

7. AIM:
To simulate and implement carry look-ahead adder using XC3S400 FPGA kit.
APPARATUS REQUIRED:
1. PC with XILINX ISE 9.1 i
2. XC3S400 FPGA kit
PROGRAM:
module CLAadder (a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire p0,p1,p2,p3,g1,g2,g3;
wire c1,c2,c3,c4;
assign p0 = (a[0]^b[0]),
p1 = (a[1]^b[1]),
p2 = (a[2]^b[2]),
p3 = (a[3]^b[3]);
assign g0 = (a[0] & b[0]),
g1 = (a[1] & b[1]),
g2 = (a[2] & b[2]),
g3 = (a[3] & b[3]),
assign c0 = cin,

8. c1 = g0 | (p0 & cin),
c3 = g2 | (p2 & g1)|(p2&p1&g0)|(p2&p1&p0&cin),
c2 = g1 | (p0 & g0)|(p1&p0&cin),
c4 = g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&cin);
assign sum[0] = p0^c0,
sum[1] = p1^c1,
sum [2] = p2^c2,
sum [3] = p3^c3,
assign cout = c4
end module
RESULT:
Thus the carry look-ahead adder was simulated and implemented using XC3S400 FPGA
kit.
SIMULATION AND IMPLEMENTATION OF CMOS GATES

9. AIM:
To simulate and implement CMOS gates using XC3S400 FPGA kit.
APPARATUS REQUIRED:
1. PC with XILINX ISE 9.1 i
2. XC3S400 FPGA kit
PROGRAM:
CMOS INVERTER:
module my_inv (input);
input in;
output out;
supply1 pwr;
supply0 gnd;
pmos (out, pwr, in);
nmos (out, gnd, in);
end module
CMOS NOT GATE:
module my_nor (a,b,out);
input a,b;
output out;
wire c;
supply1 pwr;
supply0 gnd;
pmos (c, pwr, b);
pmos (out, c, a);

10. nmos (out,gnd,a);
nmos (out,gnd,b);
end module
CMOS NAND GATE:
module my_nand (a,b,out);
input a,b;
output out;
wire c;
supply1 pwr;
supply0 gnd;
pmos (out, pwr, a);
pmos (out, pwr, b);
nmos (out,c,a);
nmos (c,gnd,b);
end module
CMOS XOR GATE:
module my_xor (a,b,out);
input a,b;
output out;
wire e,f,g;
supply1 pwr;
supply0 gnd;
assign c=~a;
assign d=~b;

11. pmos (e,pwr,c);
pmos (e,pwr,d);
pmos (out,e,a);
pmos (out,e,b);
nmos (f,gnd,b);
nmos (out,g,c);
nmos (g,gnd,d);
end module
RESULT:
Thus CMOS gates were simulated and implemented using XC3S400 FPGA kit.
SIMULATION AND IMPLEMENTATION OF PARALLEL ADDER AND SUBTRACTOR
AIM:

12. To simulate and implement parallel adder and subtractor using XC3S400 FPGA kit.
APPARATUS REQUIRED:
1. PC with XILINX ISE 9.1 i
2. XC3S400 FPGA kit
PROGRAM:
module paralleladd_sub (a3,a2,a1,a0,b3,b2,b1,b0,m,sum3,sum2,sum1,sum0,cout);
input a3,a2,a1,a0 ;
input b3,b2,b1,b0,m;
output sum3,sum2,sum1,sum0,cout;
wire cin,c1,c2,d0,d1,d2,d3;
assign cin =m;
assign d0 = a0^m,
d1 = a1^m,
d2 = a2^m,
d3 = a3^m;
full_add ff0(b0,d0,cin,sum0,c0);
full_add ff1(b1,d1,c0,sum1,c1);
full_add ff2(b2,d2,c1,sum2,c2);
full_add ff3(b3,d3,c2,sum3,c3);
end module
module full_add (a,b,c,sum,carry);

13. input a,b,c;
output sum, carry;
assign sum = a^b^c;
assign carry = (a&b)|(b&c)|(c&a);
end module
RESULT:
Thus the parallel subtractor was simulated and implemented using XC3S400 FPGA kit.
SIMULATION AND IMPLEMENTATION OF 8:3 ENCODER AND 3:8 DECODER
AIM:
To simulate and implement 8:3 encoder and 3:8 decoder using XC3S400 FPGA kit.
APPARATUS REQUIRED:

14. 1. PC with XILINX ISE 9.1i
2. XC3S400 FPGA kit
PROGRAM:
8:3 ENCODER:
module encoder8_3 (d0,d1,d2,d3,d4,d5,d6,d7,a,b,c);
input d0,d1,d2,d3,d4,d5,d6,d7;
output a,b,c;
or (a,d4,d5,d6,d7);
or (b,d2,d3,d6,d7);
out (c,d,d3,d5,d7):
end module
3:8 DECODER:
module decoder3_8 (a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0 = (~a&~b&~c),
d1 = (~a&~b&c),
d2 = (~a&b&~c),
d3 = (~a&b&c),
d4 = (a&~b&~c),
d5 = (a&~ b&c),

15. d6 = (a&b&~c),
d7 = (a&b&c);
end module
RESULT:
Thus the 8:3 encoder and 3:8 decoder was simulated and implemented using XC3S400
FPGA kit.
SIMULATION AND IMPLEMENTATION OF 1:8 DEMULTIPLEXER AND 4:1
MULTIPLEXER
AIM:
To simulate and implement of 1:8 demultiplexer and 4:1 multiplexer using XC3S400
FPGA kit.
APPARATUS REQUIRED:

16. 1. PC with XILINX ISE 9.1i
2. XC3S400 FPGA kit
PROGRAM:
1:8 DEMULTIPLEXER:
module demux1_8 (i,so,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input I,so,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0 = (i&~s2&~s1&~s0),
d1 = (i&~s2&~s1&s0),
d2 = (i&~s2&s1&~s0),
d3 = (i&~s2&s1&s0),
d4 = (i&s2&~s1&~s0),
d5 = (i&s2&~ s1&s0),
d6 = (i&s2&s1&~s0),
d7 = (i&s2&s1&s0);
end module
4:1 MULTIPLEXER:
module mux4_1 (i0,i1,i2,i3,s0,s1,out);
input i0,i1,i2,i3,s0,s1;
output out;
assign out = (i0&~s1&~s0)| (i1&~s1&~s0)| (i2&s1&~s0)| (i3&s1&s0);

17. end module
RESULT:
Thus the 8:3 encoder and 3:8 decoder was simulated and implemented using XC3S400
FPGA kit.
SIMULATION AND IMPLEMENTATION OF 8 BIT MULTIPLEXER
AIM:
To simulate and implement 8 bit multiplexer using XC3S400 FPGA kit.
APPARATUS REQUIRED:

18. 1. PC with XILINX ISE 9.1 i
2. XC3S400 FPGA kit
PROGRAM:
module multiplexer_8_bit (a,b,c);
input [7:0] a;
input [7:0] b;
output [15:0] c;
assign c[15:0] = a[7:0] * b[7:0];
end module
RESULT:
Thus the 8 bit multiplexer was simulated and implemented using XC3S400 FPGA kit.
SIMULATION AND IMPLEMENTATION OF FLIP FLOPS
AIM:
To simulate and implement flip flops using XC3S400 FPGA kit.
APPARATUS REQUIRED:

19. 1. PC with XILINX ISE 9.1 i
2. XC3S400 FPGA kit
PROGRAM:
SR FLIP FLOP:
module sr_ff (s,r,clk,q,qbar);
input s,r,clk;
output q,qbar;
reg q,qbar;
always @ (posedge clk)
begin
case ({s,r})
2’b00 : q = q;
2’b01 : q = 1’b0;
2’b10 : q = 1’b1;
2’b11 : q = 1’bx;
end case
qbar = ~q;
end
end module
D FLIP FLOP:
module d_ff (d,clk,reset,q);
input d,clk,reset;

20. output q;
reg q;
always @ (posedge reset or negedge clk)
if (reset)
q = 1’b0;
else
q=d;
end module
T FLIP FLOP:
module t_ff (t,clk,reset,q);
input t,clk,reset;
output q;
wire w;
assign w = t^q;
d_ff dff1(w,clk,reset,q);
end module
module d_ff (d,clk,reset,q);
input d,clk,reset;
output q;
reg q;
always @ (posedge reset or negedge clk)
if (reset)

21. q = 1’b0;
else
q=d;
end module
JK FLIP FLOP:
module jk_ff (j,k,clk,reset,q);
input j,k,clk,reset;
output q;
wire w;
assign w = (j^~q)|(~k&q);
d_ff dff1(w,clk,reset,q);
end module
module d_ff (d,clk,reset,q);
input d,clk,reset;
output q;
reg q;
always @ (posedge reset or negedge clk)
if (reset)
q = 1’b0;
else
q=d;
end module

22. RESULT:
Thus the flip flops were simulated and implemented using XC3S400 FPGA kit.
SIMULATION AND IMPLEMENTATION OF SYNCHRONOUS UP DOWN COUNTER
AIM:
To simulate and implement synchronous up down counter using XC3S400 FPGA kit.
APPARATUS REQUIRED:

23. 1. PC with XILINX ISE 9.1i
2. XC3S400 FPGA kit
PROGRAM:
module updowncounter (up_down,clk,reset,count);
input [1:0] up,down;
input clk, reset;
output [2:0] count;
reg [2:0] count;
always @ (posedge clk or negedge reset)
if ( reset = = 1) count <= 3’b000;
else
if (up_down = = 2’b00 || up_down = = 2’b11)
count <= count;
else
if (up_down = = 2’b01)
count <= count+1;
else
if (up_down = = 2’b10)
count <= count-1;
end module

24. RESULT:
Thus the synchronous up down counter was simulated and implemented using XC3S400
FPGA kit.
SIMULATION AND IMPLEMENTATION OF UNIVERSAL SHIFT REGISTER
AIM:
To simulate and implement universal shift register using XC3S400 FPGA kit.
APPARATUS REQUIRED:
1. PC with XILINX ISE 9.1i

25. 2. XC3S400 FPGA kit
PROGRAM:
module unishift_reg (s1,s0,PIin,LFin, RTin,clk,reset,q3,q2,q1,q0);
input s1,s0;
input LFin, RTin;
input clk, reset;
input [3:0] PIin;
output q3,q2,q1,q0;
reg q3,q2,q1,q0;
always @ (posedge clk or negedge reset)
if ( reset)
{q3,q2,q1,q0} = 4’b0000;
else
case ({s1,s0})
2’b00 : {q3,q2,q1,q0} = {q3,q2,q1,q0);
2’b01 : {q3,q2,q1,q0} = {RTin,q3,q2,q1);
2’b10 : {q3,q2,q1,q0} = {q2,q1,q0,LFin);
2’b11 : {q3,q2,q1,q0} = PIin;
end case
end module

26. RESULT:
Thus the universal shift register was simulated and implemented using XC3S400 FPGA
kit
SIMULATION AND IMPLEMENTATION OF SERIAL ADDER
AIM:
To simulate and implement serial adder using XC3S400 FPGA kit.
APPARATUS REQUIRED:
1. PC with XILINX ISE 9.1i

27. 2. XC3S400 FPGA kit
PROGRAM:
module serial_adder (count2,count1,count0,clk,a0,a1,a2,a3,a4,a5,a6,a7, a8,result,add);
input count2,count1,count0;
input clk;
input a0,a1,a2,a3,a4,a5,a6,a7, a8;
output [3:0] add,result;
reg [3:0] result,add;
always @ (posedge clk)
case ({count2,count1,count0})
3’b0000 : begin
add = a0+a1;
end
3’b001 : begin
add = add + a2;
end
3’b010 : begin
add = add + a3;
end

28. 3’b011 : begin
add = add + a4;
end
3’b100 : begin
add = add + a5;
end
3’b101 : begin
add = add + a6;
end
3’b110 : begin
add = add + a7;
end
3’b111 : begin
add = add + a8;
end
end case
end module

29. RESULT:
Thus the serial adder was simulated and implemented using XC3S400 FPGA kit
SIMULATION AND IMPLEMENTATION OF TRAFFIC LIGHT CONTROLLER
AIM:
To simulate and implement traffic light controller using XC3S400 FPGA kit.
APPARATUS REQUIRED:
1. PC with XILINX ISE 9.1i

30. 2. XC3S400 FPGA kit
PROGRAM:
module tlc (state2,state1,state0,clk,r0,y0,g0,p0,r1,y1,g1,p1);
input state2,state1,state0;
input clk;
input r0,y0,g0,p0,r1,y1,g1,p1;
reg r0,y0,g0,p0,r1,y1,g1,p1;
always @ (posedge clk)
case ({state2,state1,state0})
3’b000 : begin
r0 =1;
y0 =0;
g0 =0;
p0 =1;
r1 =1;
y1 =0;
g1 =0;
p1 =1;
end
3’b001 : begin
r0 =0;
y0 =1;

31. g0 =0;
p0 =1;
r1 =1;
y1 =0;
g1 =0;
p1 =1;
end
3’b010 : begin
r0 =0;
y0 =0;
g0 =1;
p0 =0;
r1 =1;
y1 =0;
g1 =0;
p1 =0;
end
3’b011 : begin
r0 =0;
y0 =1;
g0 =0;

32. p0 =0;
r1 =0;
y1 =1;
g1 =0;
p1 =0;
end
3’b100 : begin
r0 =1;
y0 =0;
g0 =0;
p0 =0;
r1 =0;
y1 =0;
g1 =1;
p1 =0;
end
3’b101 : begin
r0 =1;
y0 =0;
g0 =0;

33. p0 =0;
r1 =0;
y1 =1;
g1 =0;
p1 =0;
end
default : begin
r0 =0;
y0 =0;
g0 =0;
p0 =0;
r1 =0;
y1 =0;

34. g1 =0;
p1 =0;
end
end case
end module
RESULT:
Thus the traffic light controller was simulated and implemented using XC3S400 FPGA kit