This document discusses various techniques for synchronizing data transfers between an FPGA and host system, including direct memory access (DMA) FIFOs, interrupts, and handshaking. DMA FIFOs allow high-speed transfer of large amounts of data but can cause overflow or underflow errors if not implemented correctly. Interrupts eliminate polling but have higher overhead than DMA. Handshaking uses flags to coordinate data transmission and reception but requires the host to continuously poll the FPGA.

1. Lesson 7
Synchronizing FPGA and Host Data
Transfers
TOPICS
A. LabVIEW FPGA and Host Communication
B. Synchronization
C. Direct Memory Access (DMA) FIFOs
D. Lossless Data Transfer
E. Interrupts
F. Handshaking
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2. A. LabVIEW FPGA and Host Communication
• FPGA VI and host VI are inherently asynchronous
• Each VI runs independent of the other
• Data transfer synchronization needs to be implemented
based on the application needs
• To transfer large amounts of data between the target and
host at high rates you must buffer the data
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3. Synchronization and Buffering
• Synchronization—Causing tasks occur at the same time or
in unison by using clock, triggers, or events
• Buffer—An area of computer memory that stores multiple
data items
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4. B. Synchronization
• Level of synchronization depends on the application
• Synchronization not required in some slower control
applications
− For example, if the data acquisition loop is faster than the
control loop, the control loop reads the most recent value
• Synchronization required to acquire and transfer lossless
data at a known rate
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5. Asynchronous vs. Synchronous
• Asynchronous Applications
− Applications that don’t require tight synchronization for control
or data processing
− Timing performed on the FPGA, but no synchronization to the
host application
− Most recent data is okay, many control applications
• Synchronous Applications
− Synchronization required between FPGA VI and host VI
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6. Synchronous Applications
• Timing control
− Timing from the FPGA/acquisition controls the timing/loop rate
of the host VI, and vice-versa
• Synchronized Data Transfer
− Synchronization transfers/streams data from acquisition to host
VI for processing and logging
− Lossless data transfer
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7. Synchronization Methods
• Direct Memory Access (FIFO)
• Interrupts
• Handshaking
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8. C. Direct Memory Access (DMA) FIFOs
Data Buffering
• To transfer larger amounts of data at high rates between the
target and the host you must buffer your data.
• The best way to buffer data is by using Direct Memory
Access (DMA) data transfer methods.
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9. Direct Memory Access (DMA) FIFOs (continued)
• Transfers data from FPGA directly to memory on the RT controller
through bus mastering.
• Streams large amounts of data.
• Provides better performance than using local FIFO and reading
indicators.
• Host processes data while FPGA transfers data to host memory.
• Without DMA, processor must read data.
• Consists of two parts—FIFO part and host part.
• FPGA writes data one element at a time to the FPGA memory.
• DMA engine transfers data along PCI bus to host memory.
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10. Demonstration: Target-to-Host DMA FIFO
Explore how the FPGA transfers data to the host.
GOAL
<Exercises>LabVIEW FPGADemonstrations
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11. Demonstration: Host-to-Target DMA FIFO
Explore how the host transfers data to the FPGA.
GOAL
<Exercises>LabVIEW FPGADemonstrations
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12. Creating DMA FIFOs
• Create DMA FIFO the same way as FPGA FIFOs
− Right-click target
− Select New»FIFO
− Choose Target to Host
or Host to Target as
Type
• All DMA FIFOs are
U32 data type
− Must convert to
and from U32.
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13. Writing Data to a Target-to-Host DMA FIFO
Drag FIFO from Project Explorer window.
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14. Writing Data to a Target-to-Host DMA FIFO
(continued)
FIFO Write Function
• Element—Inputs the data element to be stored.
• Timeout—Inputs the number of clock ticks the function waits
for available space in the FIFO if the FIFO is full. The default
is 0, or no wait. A value of –1 prevents the function from
timing out.
• Timed Out?—Returns True if space in the FIFO is not
available before the function completes execution.
− If Timed Out? is True, the function does not add Element to the
FIFO.
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15. Reading Data from a Target-to-Host DMA FIFO
Read a DMA FIFO in the
host:
1. Open a reference to the FPGA
2. Add an Invoke Method function
3. Choose the DMA FIFO»Read
method
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16. Reading Data from a Target-to-Host DMA FIFO
(continued)
Read a DMA FIFO on the host:
• Number of Elements
− Function completes when elements are
read or timeout is reached
− Same overhead regardless of the number of elements; read
more elements if host is too slow
• Timeout—Time to wait before timeout (–1 = indefinite wait;
Default is 5,000 ms)
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17. DMA FIFO with Blocking
Implementing a DMA FIFO with blocking:
• User specifies number
of elements
• Best method when
input/output rate is known
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18. DMA FIFO with Polling
Implementing a DMA FIFO with polling:
• Acquires as many samples
as are currently available
• Best when the
input/output rate is
unknown
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19. Writing Multiple Channels
Writing multiple channels of data to a DMA FIFO by
interleaving
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20. Reading Multiple Channels
Reading multiple channels from a DMA FIFO in the host
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21. D. Lossless Data Transfer
• Lossless Application
• Overflow—DMA Full?
• Underflow—Check for –50400
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22. Overflow
Overflow—too many data points for buffer, may lose data
• Acquire data slower
• Increase number of elements to read on the host
• Increase the rate that the host reads data
• Increase buffer sizes on FPGA and host
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23. Demonstration: Target to Host DMA FIFO –
Overflow
Explore how overflow of the DMA FIFO occurs if the
RT host VI is too complex.
GOAL
<Exercises>LabVIEW FPGADemonstrations
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24. Underflow
Underflow—not enough data to read, FIFO read times out
•
Increase timeout
•
Read data less often
•
Read smaller sets of elements
•
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25. Demonstration: Target to Host DMA FIFO –
Underflow
Explore how underflow occurs when the DMA FIFO tries to
read data before it is available.
GOAL
<Exercises>LabVIEW FPGADemonstrations
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26. Exercise 7-1: DMA-Based Data Transfers
Observe how DMA-based handshaking works.
GOAL
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27. E. Interrupts
• Send a trigger from the target to the host application.
• Why use an interrupt?
− Eliminate polling
− Allow host to perform other operations while waiting for the
Interrupt signal
• Communicate over a physical hardware line
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28. Advantages of Interrupts
• An interrupt requires execution of a low-level driver on the
host, so a host can process more polling operations/s than
interrupts/s
• Comparison statistics for a Networked RIO Device:
− A single poll requires 10 s
− An interrupt requires about 250 s
• Use Interrupts when FPGA sends data less often and host
must do other processing
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29. Implementing an Interrupt
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30. Implementing an Interrupt (continued)
Interrupt Express VI
• IRQ Number
− Specifies which logical interrupt (0 – 31) to assert
− Default is 0
• Wait Until Cleared
− Specifies if this VI waits until the host VI acknowledges the
logical interrupt
− Default is False
• Wait Until Cleared as True causes jitter due to dependency
upon the host VI
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31. Host and Interrupts
• Host must acknowledge interrupts
• Use Wait on IRQ and Acknowledge IRQ methods
− IRQ Number(s)—specifies the logical interrupt or array of
logical interrupts for which the function waits
− Timeout (ms)—specifies the number of milliseconds the VI
waits before timing out. –1 = infinite timeout
− Timed Out—returns TRUE if this method has timed out
− IRQ(s) Asserted—returns the asserted interrupts. Empty or –1
array indicates that no interrupts were received
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32. Acknowledge IRQ Method
• Acknowledges and resets to the
default value any interrupts that
occur
− Wire after the Wait on IRQ method
− IRQ Number(s) specifies the logical interrupt or array of logical
interrupts for which the function waits
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33. Interrupt Example
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34. DMA FIFO with Interrupts
Implementing a DMA FIFO with an interrupt
• Prevents the CPU from polling the DMA FIFO to see if elements have
arrived
− Least resource intensive DMA FIFO transfer method
− Slowest DMA FIFO transfer method due to IRQ delay
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35. Exercise 7-2: Interrupt-Based Handshaking
Observe an example of how interrupt-based handshaking
works.
GOAL
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36. F. Handshaking
Handshaking—Checks that a receiving device is ready to
receive or a transmitting device is ready to transmit
• Handshaked synchronization—occurs when two or more
devices act in sequence
• Host uses Boolean controls and indicators (data available
and data read flags) on the target to coordinate operations
• Requires polling
• Assures that all data that is sent is also received
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37. Handshaking Process
1. FPGA acquires data
and writes values to Array
2. FPGA writes True to
Data Available
3. When Data Available
is True, host reads data
4. After reading data,
host writes True to
Data Read
5. FPGA loop iterates
when Data Read is True
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38. Quiz
1. Which of the following are 2. What error are you likely
methods of transferring to get if you create a DMA
data from the target to the FIFO that is too small?
host? a. Underflow
a. Handshaking b. Overflow
b. Target-scoped FIFO c. Evenflow
c. Interrupt
d. DMA FIFO
e. FTP
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39. Quiz
3. What happens when a 4. Which technique requires
DMA FIFO has an the host VI to use polling?
underflow condition? a. Handshaking
a. The FPGA resets b. Interrupts
b. The FIFO Read throws c. DMA FIFO
Error –50400
c. The Timed Out? indicator
latches true
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