1. MODELING OF INTERCONNECT DIELECTRIC LIFETIME UNDER STRESS CONDITIONS AND NEW EXTRAPOLATION METHODOLOGIES FOR TIME-DEPENDENT DIELECTRIC BREAKDOWN Gaddi S. Haase , Joe W. McPherson Texas Instruments, Dallas, TX, USA 4E.2
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7. The actual line-to-line spacing distribution in a 65nm technology comb-comb test structure The observed spacing distributions, from many cross-sectional electron micrographs for each test structure, were fitted with asymmetric normal distributions (solid curves) for ease of use in the simulation. M1 M2 M1
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11. Simulated apparent TDDB Using DUTs from three spacing-distribution zones. However, the “true” used in this simulation was 2.0 The “apparent” is only ~1 Simulated data Note: The true is dictated by the actual material variation
12. At low voltage, appears again as 2.0 Extending the simulation to operating voltage : Simulated data At operating voltages, the spacing variations do not affect the lifetime uncertainty as much as at test voltages ! The “true” value can be used for product reliability assessment
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16. Evaluating the true with V-ramp tests Simulated data Simulated data Using V-ramp to breakdown at two ramp rates , s i / can be extracted at F =63%, and used to derive from V bd,63% vs. area curves.
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Notes de l'éditeur
Quick Low-k : leaky, traps Interfaces with ESL or cap span between Cu lines Thickness like gate oxide 2 decades ago
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