32. Analog Data Conversion & Serial Link IP Roadmaps 2007-01 Sigma-Delta Codec RSDS TX 3-channel DAC Note : The right edge of each block denotes the IP’s formal release date. For more details, p lease visit our website at: www.faraday-tech.com ADC DAC LVDS TX / RX 130nm 16-bit Audio Codec 10 2004-07 10 2005-01 4 7 10 2006-01 4 7 10 7 0.18µm 10-bit 80MHz ADC 130nm 8-bit 125MHz ADC 0.25µm 10-bit 150MSPS 3-channel DAC 0.18µm 8-bit 44MSPS DAC 130nm 12-bit 100MSPS DAC 0.25µm 16-bit Audio Codec 0.18µm 10-bit 150MSPS 3-channel DAC 130nm 10-bit 150MSPS 3-chanel DAC 0.25µm 18-bit Audio Codec 0.18µm 16-bit Audio Codec 0.25µm 6-bit 44MHz 130nm 10-bit 80MHz ADC 0.35µm RSDS 0.35µm LVDS 0.25µm RSDS 0.25µm LVDS 0.18µm LVDS 0.25µm mini LVDS 0.18µm 1.8V LVDS 130nm LVDS 130nm 0.18µm 0.25µm 0.35µm 90nm 0.15µm
33. USB IP Roadmap 130nm 0.18µm 0.25µm 0.35µm 90nm FPGA 0.15µm FPGA USB2.0 2-port Host PIE FUSBH210 Legend Description : HS : High Speed SP : Standard Performance * * * Note : The right edge of each block denotes the IP’s formal release date. For more details, p lease visit our website at: www. faraday-tech. com USB 2.0 OTG PHY USB 2.0 OTG PIE USB 2.0 Host PIE 90nm USB 2.0 OTG PHY USB2.0 2-port PHY 130nm USB 2.0 2-port PHY FPGA USB2.0 Host PIE FUSBH200 FPGA USB2.0 OTG PIE FOTG200 0.25 µm USB2.0 OTG PHY 130nm USB2.0 OTG PHY HS 130nm USB2.0 OTG PHY SP 0.18 µm USB 2.0 Device PHY v36 USB 2.0 Device PHY
34. Serial-ATA IP Roadmap Serial-ATA Controller Serial-ATA PHY Note : The right edge of each block denotes the IP’s formal release date. For more details, p lease visit our website at: www.faraday-tech.com 130nm 0.18µm 0.25µm 0.35µm 90nm FPGA 0.15µm FPGA Serial-ATA Controller With AHB I/F 130nm 3Gbps SATA PHY 130nm Multi-Port SATA PHY
35. PCI Express IP Roadmap Note : The right edge of each block denotes the IP’s formal release date. For more details, p lease visit our website at: www.faraday-tech.com PCI Express Controller PCI Express PHY FPGA PCI-Express Controller End-point (PIPE) 130nm Multi-lane PHY x 4 lane 130nm Single-lane PHY x 1 lane 0.18µm Single lane PHY x 1 lane 130nm 0.18µm 0.25µm 0.35µm 90nm FPGA 0.15µm
36. Ethernet Roadmap 10/100 Ethernet PHY Legend Description : HS : High Speed * * Note : The right edge of each block denotes the IP’s formal release date. For more details, p lease visit our website at: www. faraday-tech. com 130nm 0.18µm 0.25µm 0.35µm 90nm 0.15µm 130nm HS 10/100 Ethernet PHY 0.18µm 10/100 4- port Ethernet PHY 0.25µm 10/100 Ethernet PHY
37. Digital IP Roadmap Communication Peripheral 2003-01 4 7 10 2004-01 4 7 10 2005-01 MS Pro Card Controller LCD Controller 10 / 100 MAC Gigabit MAC TV Encoder MPEG4 Encoder / Decoder DES / 3DES Security Engine Wireless LAN 802.11a / b / g MAC / BBP DDRI Controller Note : The right edge of each block denotes the IP’s formal release date. For more details, p lease visit our website at: www.faraday-tech.com DDRII Controller Multimedia
38. Faraday CPU Roadmap Note : Left and right edges indicate Tape out and Silicon proven schedule respectively . For more details p lease visit our website at: www. faraday-tech. com Legend Description : HS : High Speed LL : Low Leakage * * * * * Clock (MHz) 200 300 400 500 800 0.18µm FA510 0.18µm FA526 130nm HS FA526 HS 130nm FA501 130nm LL FA526L 130nm HS FA626 90nm HS FA626 130nm 0.18µm 0.25µm 0.35µm 90nm FPGA 0.15µm
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40. DSP Roadmap Note : The right edge of each block denotes the IP’s formal release date. For more details, p lease visit our website at: www.faraday-tech.com 2004-7 10 2005-01 4 7 10 2006-01 4 7 10 2007-01 0.18µm FD216_H90A Hardcore 0.18 µm FD216_HA0A Hardcore (w/ mailbox) 0.25µm 130nm 0.18µm Co-Processor 130nm Fusion FD216 130nm Fusion FD230-24 130nm 0.18µm 0.25µm 0.35µm 90nm FPGA 0.15µm