This document summarizes a research paper that proposes a new CMOS-based cascode current mirror circuit design for analog signal processing applications. The paper begins with background on current mirrors and their importance in analog circuit design. It then reviews traditional current mirror configurations and discusses design parameters that impact performance. The document introduces a new cascode current mirror circuit and provides equations to model its behavior. Simulation results are presented and analyzed, showing the new design achieves high accuracy, output swing and low power dissipation compared to traditional approaches. In conclusion, the proposed circuit is well-suited for low-voltage analog signal processing.

1. International JournalElectronics and Communication Engineering & Technology (IJECET), ISSN
International Journal of of Electronics and Communication
IJECET
Engineering & Technology (IJECET) Volume 2, Issue 2, May-July (2011), © IAEME
0976 – 6464(Print), ISSN 0976 – 6472(Online)
ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online)
Volume 2, Issue 2, May – July (2011), pp. 01-07 ©IAEME
© IAEME, http://www.iaeme.com/ijecet.html
A NEW APPROACH FOR DESIGN OF CMOS BASED CASCODE CURRENT
MIRROR FOR ASP APPLICATIONS
Rajinder Tiwari1, R. K. Singh1, Ganga Ram Mishra2
1
Department of Electronics & Communication Engineering, Kumaon Engineering
College, Dawarahat (Almora), Uttarakhand
2
Department of Electronics & Communication Engineering, Amity School of
Engineering & Technology, Amity University Uttar Pradesh, Lucknow
trajan@rediffmail.com rksinghkec12@rediffmail.com grmishra@rediffmail.com
ABSTRACT
The current mirror is the core structure for analog, digital and mixed signal circuits
and thus, the performance of the analog devices mostly depends on it’s characteristics
i.e. for low voltage analog CMOS circuits, a low voltage current mirror circuit is
required. The topology of the circuit is an upgraded structure of the constant current
source that provides a highly precise output operating over a wide range of power
supply. This circuit basically operates on the principle that if the gate-source voltage
of the two identical MOS transistors is equal, then the channel currents should be
equal. The current mirror circuit plays a dominant role in the design procedure of the
active elements and devices like operational amplifiers, current conveyors, current
feedback amplifiers and differential amplifier. In the present work, we propose an
innovative cascode current mirror circuit that can be used in the design of various
active devices for better and enhanced performance. This circuit has been simulated
using pSPICE software simulator with level 3 parameters for 0.13 micron CMOS
technology.
KEYWORDS
Current Mirrors, CMOS Integrated Circuits, Analog CMOS Circuits, Analog Devices,
MOS Transistor, Novel CM, Channel Current).
1. INTRODUCTION
A current mirror is a circuit that is designed to provide a mirror image of the
current flowing through one active device simply by controlling the current in another
active device, keeping the resultant output current as constant regardless of changes in
the load. Due to this property, it is considered as the main building blocks of analog
and mixed-signal integrated circuits. The current mirror can be configured as a simple
current mirror circuit and a cascode current mirror circuit. The cascode current mirror
circuit is more commonly used in the various integrated circuits since this provides a
better performance in terms of the operating voltage, output swing, etc. It is normally
desired that the input voltage drop should be minimum at the input terminals of the
circuit particularly in case of current sensing circuits [1]. The dynamic biasing
techniques are used so as to keep the cascoded active devices always operate in the
saturation region so that the high precision and high output impedance can be
maintained over a large operating range. It means that in the process of biasing of the
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2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 2, Issue 2, May-July (2011), © IAEME
circuit and active devices, the performance of current mirror must be focused on the
accuracy and output impedance of the circuit performance [2]. In case of high speed
applications, the settling time of current mirror circuit plays an important role in order
to enhance the overall efficiency of the application in addition to the accuracy and the
output impedance. It means that in case of the analog circuits design, the majority of
the research works is mainly focused on the accuracy, output impedance and the
settling time. Thus, based on this, one can have the cascode current mirror [3] as the
traditional current mirror that is used to increase the output impedance of the circuit,
the regular-gate cascode (RGC) current mirror [4] uses active-feedback circuit so as to
increase the output impedance and the improved active-feedback cascode current
mirror (IAFCCM) [5] that also enhances the output impedance, accuracy. The
linearity of the CMOS current mirror circuit has got the fundamental limitation in the
operation of the current mode signal processing applications due to the matching
properties of the transistors in the mirror i.e. mismatch in geometric sizes, in the
transconductance parameter of the transistors and the operating conditions of the
current mirror transistors particularly, the differences in the drain-source voltages of
the input transistor and output transistor. This mismatch can be removed with proper
circuit techniques of cascading that ensures the identical operating conditions for the
transistors [6].
2. BASIC CURRENT MIRROR CONFIGURATIONS
The basic need of a current mirror circuit is to provide a constant voltage at the input
of an active device so as to avoid the errors introduced in the signal due to the
fluctuation of the input signal, thereby, lowering the mirror input impedance which in
turn minimizes the loading effect on the previous stage of the circuit. If the load
impedance of the device is not sufficiently low, the device will suffer large drain-to-
source voltage variations, which through the channel length modulation effect will
cause a systematic mismatch error between the input and output currents of the
mirror [7]. This sort of problem can be avoided by using the cascode configuration of
the current mirror circuit. The idea behind cascode structure is to convert the input
voltage to a current and apply the resultant signal to the common source stage [6-10].
The overall effect on the performance of the cascode circuit with one device operating
in the sub threshold and the other device operating in the active region could result in
a very high gain stage with low power dissipation [13, 14]. The basic advantage of
folded structure is that it provides the choice of the voltage levels because it does not
“stack” the cascoded active device on top of the input device but with a little higher
power consumption [16].
Fig. 1 Basic cascode configurations of current mirror: Active, Cascode, Regulated
cascode output, Active regulated cascode, basic circuit and basic cascode
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3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 2, Issue 2, May-July (2011), © IAEME
The figure 1 shows the various configurations of the current mirror circuit which is
quite frequently used in the analog signal processing (ASP) applications. The concept
of the active cascode current mirror has been used simply to maintain a constant
voltage at the input of the circuit so as to avoid the current subtraction error [15]. This
technique results in making the voltage (VGS) of the input transistor of the current
mirror independent of the voltage (VDS) that is biased to remain constant which in
turn reduces the input impedance and minimize the loading effect of the circuit. The
systematic mismatch introduced between the input and output currents of the circuit
can be avoided with the use of the cascode current mirror configuration shown in fig
1(b) but with a smaller output voltage swing which in turn requires a high input
voltage drop for better accuracy [16 - 18]. The regulated-cascode current mirror
configuration as shown in fig l(c) is used to keep the voltage (VDS) of the transistor of
the circuit as constant thereby, enhances the output impedance of the circuit with a
precise voltage swing at the input of the circuit. The configuration shown in fig 1(c) is
basically a combination of the two different configurations with the desired features
i.e. low input impedance and very high output impedance [15-16]. The operational
analysis of the current mirror circuit is basically required to ensure that equal drain
voltages are provided for the input and output transistors for a better performance of
the circuit i.e. the circuit is highly stable with low input and high out impedance and
high output voltage swing [19 - 22]. The mathematical analysis of the cascoded
current mirror circuit can be easily determined with the use of the following
expressions and the formulae of the active devices of the circuit voltages and the
currents [23].
2iD1
vGS =VT1 + =>
β1(1+λ1vDS1)
β2
iD2 = (vGS −V 2)2(1+λ2vDS2)
T
2
β2 2iD1
iD2 = (VT1 −V 2 +
T )2(1+λ2vDS2)
2 β1(1+λ1vDS1)
β2 2iD1 2iD1
iD2 = ( +∆VT2 −2∆VT )(1+λ2vDS2)
2 β1(1+λ1vDS1) β1(1+λ1 +vDS1)
∆β
iD2 (1+ )iD1 −∆VT 2βiD1
β
The output current of the circuit can be determined with the below given formula i.e.
[24]
2
I out =
1 2
µ n C oxW / L N R 2 S (1 − )
K
Where K is the ratio of the size the two active devices used to provide the cascoded
path to the circuit. In addition to these, there are certain more parameters that affect
the performance of the current mirror circuit i.e. by putting λVDS1= 0, one can solve
the equations as
W
( )2
IOut = I Re f L (1 + λV )
DS 2
W
( )1
L
1
rout = rds 2 =
λ I Out
W 2
I Out ( µCox)2 ( L )2 (VGS − VTh 2 ) (1 + λVDS 2 )
=
I Re f W
(µ Cox)1 ( )1 (VGS − VTh1 )2 (1 + λVDS1 )
L
Thus, with this discussion one can easily put forward that the parameters affecting the
performance of the circuit are channel length modulation, offset between the threshold
voltages, imperfect geometrical matching of the active devices, technological
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4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 2, Issue 2, May-July (2011), © IAEME
parameters mismatch and stray resistances. It means that the scope of the study of the
cascoded current mirror is based on the performance of these parameters which in
turn determine the output efficiency of the circuit in various ASP applications [25 -
30].
3. PROPOSED CMOS CASCODE CURRENT MIRROR CIRCUIT
The proposed CMOS based CCM circuit is shown in the below fig (3). The basic
concept of the cascode structure is to convert the input voltage to a current, and then
fed this current to a common source with one device operating in sub threshold and
the other device operating in active region. This approach in turn offers a very high
gain in addition to low dissipation. It basically consists of the transistors M1 to M12,
with the transistors M5 and M6 provides the cascode structure desired for this circuit.
The transistors are biased in such a way that it has got less effect on the output swing
of the circuit with an enhancement in the output impedance operating in the sub volt
region [31 - 35]. The proposed circuit is simulated for 0.13 µm technology with level
3 parameters. The input voltage (V1) and the biasing current (I3) are assumed in the
range of 5 volts and 1nA so that it can assured a low input operating voltage in the
range of fraction of volt. As shown in the fig (3), this proposed CCM circuit improves
the output impedance, stability and accuracy without any biasing and external
compensation of the transistors that in turns reduces the power dissipation of the
circuit. The resultant output impedance of the CCM circuit can be estimated with the
use of following equations i.e. with the use of the transconductance and the channel
conductance of the active devices.
1
V 1 = io u t
g d n 4
io u t = g m n 3 v g s , n 3 + g d n 3 v d s , n 3
g m n 7
io u t = g m n 3 ( − 1 ) v 1 + g d n 3 ( v o − v 1 )
g d n 7
g m n 3 g d n 3 g m n 3 g m n 7
io u t (1 + + + ) = g d n 3 v o
g m n 4 g d n 4 g d n 4 g d n 7
g m n 3 g d n 3 g m n 3 g m n 7
(1 + + + )
v o g m n 4 g d n 4 g d n 4 g d n 7
=
io u t g d n 3
v o g m n 3 g m n 7
≅
io u t g d n 3 g d n 7 g d n 4
g m n 3 g m n 7 1
R o u t =
g d n 3 g d n 7 g d n 4
Fig. 2 Proposed Cascode Current Mirror
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5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 2, Issue 2, May-July (2011), © IAEME
4. SIMULATION RESULTS & CONCLUSION
The simulation results of the proposed CCM circuit are shown in the fig (3) and fig
(4). The D.C. performance of the circuit is simulated with the level 3 modeled
parameters and the desired behaviour of the current mirror has been depicted i.e. the
input has been copied at the output with minimum delay in the range of µsec. The
input operating voltage is applied to the transistor M7 and the output has been
obtained across the gate terminal of the transistor M11. Based on the same modeled
parameters of the transistors, the transient analysis i.e. the performance of the
proposed circuit has been studied with respect to the time in the presence of the
amount of noise contributed, and the simulated result of the same is shown in fig (4).
Thus, based on the results obtained for this proposed CCM circuit, it has been
deduced that this circuit provides a better accuracy with high output swing and low
power dissipation. This proposed circuit requires fraction of volt signal to operate
satisfactorily. The transient analysis of the proposed circuit in fig (4) shows that it
depicts the exact behaviour of the current mirror or source i.e. provides the mirror
image of the input with minimum possible delay and distortion introduced due the
presence of noise. The performance of the proposed CMOS based CCM circuit can be
supported to the best with the help of the fig (5) that provides the input and output
signal behaviour with minimum distortion.
Fig. 3 D.C. Analysis Fig. 4 Transient Analysis Fig. 5 Performance Analysis
ACKNOWLEDGEMENTS
The authors are thankful to Prof. D. S. Chauhan (Vice Chancellor, UTU) for
providing the environment for this work and Mr. Aseem Chauhan (Additional
President, RBEF), Major General K. K. Ohri, AVSM, Retd. (Director General,
AUUP, Lucknow campus) and Prof. S. T. H. Abidi (Director, ASET), Brig. Umesh K.
Chopra, Retd. (Dy. Director, ASET) for their kind cooperation, motivation, kind and
most valuable suggestions.
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