Remote sensing satellite data demodulation and bit synchronization 2

International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN
0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME
1
REMOTE SENSING SATELLITE DATA DEMODULATION AND BIT
SYNCHRONIZATION
A.N.Satyanarayana1
, Dr Y. VenkataRami Reddy2
and B.C.S.Rao3
1
M. Tech , Scientist, Indian Space Research Organization, working at Satellite Data Reception
Station/ SD&MSD, NRSC, Hyderabad, India
2
Ex Vice Chanciller JNTU, A.P.
3
Divisional Head, Servo Drive & Mechanical Systems Division, Satellite Data Reception Station,
Indian Space Research Organization, Hyderabad, India
ABSTRACT
This paper presents the analysis of Remote sensing Satellite Data reception chain and its sub
systems developments and improvements for error free data acquisition. In the operational mode,
the remote sensing satellite video data being highly dynamic and un-known The current day remote
sensing satellites are equipped with state of the art sensors having finest spatial and spectral
resolutions and imaging capabilities to cater to the diversified applications for the earth resources
management. The advancement in the sensor technology has brought in a sea change in the satellite
communication systems in order to handle these ever-increasing data rate requirements. As the
usable spectrum to transmit this information is large, more efficient modulation schemes like QPSK
modulation, having more bandwidth and power efficiency are being used.
This paper deals with the design and implementation aspects of high data rate digital
demodulators. The high data rate digital Demodulator is a complicated processing element in the
entire ground reception system, which includes both hardware and software. The design of digital
demodulator must cater to flexibility in processing different modulation schemes, pulse shapes and
data rates. The demodulator complexity is directly related to the design of carrier regeneration
circuitry within the demodulator, which in turn depends on the complexity of the modulation type
used. With the advancement of the VLSI technology, coupled with the flexibility of digital signal
processing algorithms, it is convenient to implement the design of high data rate digital demodulator
with as much digital processing as possible.
The high data rate digital demodulator performs IF amplification, filtering and analog to
digital conversion of the received IF signal followed by Digital vector demodulator and symbol
timing recovery. The basic design strategy includes a configurable data rate QPSK demodulation
circuitry utilizing the flexibility of FPGA /DSP implementation. The Performance of the
Demodulator and bit synchronizer is evaluated using MATLAB simulation tools. The demodulator
is intended to give the BER performance of 1X10-6 at an Eb/No threshold within 2 dB of the
theoretical value.
INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN
ENGINEERING AND TECHNOLOGY (IJARET)
ISSN 0976 - 6480 (Print)
ISSN 0976 - 6499 (Online)
Volume 4, Issue 3, April 2013, pp. 01-12
© IAEME: www.iaeme.com/ijaret.asp
Journal Impact Factor (2013): 5.8376 (Calculated by GISI)
www.jifactor.com
IJARET
© I A E M E

2
Index Terms: Demodulator, Bit Synchronizer, Bet error rate, Satellite link, PN Sequence Pattern,
Sensor data, Filters.
I. INTRODUCTION
Atypical Remote sensing satellite Earth station is shown in figure 1. The system in this
example has both an uplink and downlink signal path, with a space satellite in between. With regard
to the testing of this system, the BERT is, for all practical purposes, “the centre of the universe”.
The BERT is the instrument that generates a PN sequence pattern digital signal, which in turn is
modulated onto a subcarrier and then placed onto an RF carrier by the up converter.
The modulated carrier is then down converted and the signal is received by the down link
chain, where it is amplified by a Low Noise Amplifier (LNA) and down converted to an
Intermediate Frequency (IF). The main carrier on the IF signal is demodulated by the IF Receiver
producing a subcarrier containing the original digital test signal (PN Sequence data) created by the
BERT. The clock and data of the digital test signal are recovered by the Bit Synchronizer and
presented to the BERT. Coming full circle, this recovered down link data is compared with that sent
in the uplink. The BERT counts the number of bit errors in the recovered signal and provides the
operator with a Bit Error Rate, or BER. This BER measurement is one of the fundamental
parameters that characterize the overall performance of the Remote Sensing Satellite Earth Station,
and of many of its components.
1.1 Data Reception
NRSC has got its Earth Station at shadnagar. Basically an Earth station Links the Space
segment with the Ground segment. An Earth Station receives signals from satellite; it consists of
Tracking chain and Data chain. The tracking chain is made use to track the Satellite and align the
Antenna in the direction of the satellite correspondingly to its antenna moments. The data chain is
used for the reception of the data. The earth station makes use of Microwave frequencies and
especially of X-band (8-12GHZ) and S-band (4-8GHZ0 for the data acquisition.
The major functions of remote sensing satellite ground station system are:
• Reception of good quality of data acquisition of satellite to loss of satellite.
• Acquiring and tracking of satellite pass.
• Local loop checks.
• Data Demodulation and Bit Synchronization.
• Suitability for automation for analysis of operation and maintenance.
• Receive and archive the high data rate digital information with designed data quality in real
time.
• To track data mainly in X or S band.
Real time data archiving and quick look monitoring of the data quality.
This paper analyzes the key issues in the reception of data quality, the requirements for error free
data quality and tracking the target with real time monitoring all the parameters etc, .specially
keeping in mind the present trend towards the importance of real time satellite sensor data.
The study describes the technique of The High data rate digital demodulator. This consists of a Front
end IF band pass filter, AGC amplifier and IQ demodulator followed by Dual Channel 8 bit analog
to digital converter. The digitized signal is then applied to the digital Costas loop that performs
Coherent carrier recovery along with symbol detection function of the demodulation process.

3
1.2 BRIEF DESCRIPTION OF THE GROUND STATION SYSTEM
The ground station system configuration is explained with reference to the block diagram in Fig.1.
Figure 1 Block Diagram of Data Acquisition
The system consists of a diametric parabolic reflector antenna with cassegrain feed, mounted
over an EL over AZ driven pedestal. The feed and front-end system realizes single channel
monopulse signal tracking and data reception in X – Band frequencies. The sum and difference
channel signals from the front-end system are fed to a five channel synthesized down converter are
driven to the control room, wherein, after the amplitude equalization, the sum channel is fed to the
data demodulation while the difference channel signal is fed to the tracking receiver.
The data and clock signals from the demodulator and Bitsynchronisers are fed to the archival
systems during the pass. The tracking video output, corresponding to the antenna offset information
in Azimuth and Elevation axes, from the tracking receiver is fed to the antenna control unit.
The antenna control unit has several operational modes to control the antenna movement.
The unit drives the antenna in auto track mode during the satellite pass with programme tracking
mode operating as backup.
The servo system is a dual drive system with torque bias arrangements to avoid antenna
backlash during tracking.
A typical remote sensing satellite Earth station is shown in figure 1. The system in this
example has both an uplink and downlink signal path, to the testing of this system, the BERT is, for
all practical purposes, “the center of the universe”. The BERT is the instrument that generates a
special digital test signal which in turn Up converted to a required remote sensing satellite
frequency and it ir being passed through the total receive chain components and the BERT
generated special digital signal is being received by the Built in receiver of BERT system. Coming
full circle, this recovered down link data is compared with that sent in the uplink. The BERT counts
the number of bit errors in the recovered signal and provides the operator with a Bit Error Rate, or
BER. This BER measurement is one of the fundamental parameters that characterize the overall
performance of the earth station, and of many of its components.
2. The Implementation of High data Rate Digital Demodulator
The design details of each of the functional blocks are presented below:
IF Band Pass Filter : The down converted IF data signal is passed through a band pass filter to
reject noise and to limit the data bandwidth in order to prevent aliasing associated with the analog
to digital converter. The IF band pass filter is basically a Nyquist filter centered at the carrier
frequency of the IF signal. The single sided transfer function of the band pass Root Raised Cosine

4
(RRC) filter is identical to the two sided base band frequency response of the equivalent base band
filter with it’s center frequency shifted from zero Hertz to the carrier frequency Fc Hz. Thus an
important difference between base band RRC filter and band pass IF RRC filter is that the IF
version has a bandwidth twice that of the base band filter. The anti-aliasing filter band width must
be B =2/Symbol. In the Satellite transmitter and the ground station receiver, the RRC band pass filters
are always implemented in the Intermediate frequency section of the transmitter or receiver. The IF
Filter used in the proposed design is a 0.05 dB Chebyshev design lumped Component, Micro
miniature Band pass filter , The Center frequency of the IF filter is at Fo =720MHz with +/-
90MHz pass band around center frequency. The maximum group delay variation within the pass
band is about 1ns.
The insertion loss at the center frequency of the filter is determined by the equation:
Loss = ( (Loss Constant) (No. Of Sections + 0.5) +0.3)
% Bandwidth
The Attenuation for rejection frequencies from Center Frequency
= Reject Frequency - Center Frequency
% bandwidth
Figure 2
The High data rate digital demodulator (Fig.2) consists of a Front end IF band pass filter, AGC
amplifier and IQ demodulator followed by Dual Channel 8 bit analog to digital converter.
The amplitude vs frequency response and group delay vs frequency response of the IF band pass are
shown below, figure-3.
Figure 3 Amplitude vs Frequency response

5
2.1 Automatic gain Control amplifier
An Automatic Gain Control (AGC) amplifier is used in the front end of the Digital QPSK
demodulator to provide a constant carrier amplitude level over a wide dynamic range of the input
signal. In the normal operation , the input Signal level differences arise from downlink fading due
to rain attenuation, sporadic interferences or multipath effects etc. These variations can be as much
as 12dB within the duration of the Line of sight data reception for the remote sensing satellites.
These amplitude variations will give rise to a kind of AM to PM conversion of the modulated signal
at the input of Carrier recovery PLL circuit. This causes significant variations of all the loop
parameters and affect the loop performance and locking phenomena. Hence it is essential to
maintain a constant amplitude for the modulated QPSK signal in order to have a distortion free
demodulated base band output.
In the AGC amplifier circuit the peak power of the PSK signal is detected and fed back to the
amplifier, changing it’s gain until the output level reaches a predetermined constant value. AGC
measures the overall strength of the signal and automatically adjusts the gain of the receiver to
maintain a constant level of output.
Figure-4 Block diagram of Automatic Gain Control amplifier
When the signal is strong, the gain is reduced, and when it is weak, the gain is increased, or
allowed to reach its normal maximum. The response time of the AGC circuit should be carefully
designed, so that the input signal stabilizes well before the PLL acquisition time. Normally the
AGC time constant is chosen to be about 1 mille second for real time data receivers in remote
sensing ground stations.
2.2 Analog to Digital Converter module.
The filtered analog signal is sampled by the A/D converter at a rate of fs equal to 4 times the
data rate. The analog to digital converter converts the received wideband IF signal into 16 bit
digital samples. Clock signal applied to the A/D converter is controlled by the Numerical controlled
Oscillator, which in turn is the integral multiple of the bit rate.
The only limitation to the data rate of operation in the design of Digital demodulator is the
A/D converter. It is desirable to use parallel and Multi rate algorithms to allow all the traditional
functions of a digital demodulator to be performed within a single CMOS VLSI ASIC at the
Nyquist data rate. This system-on-a- chip methodology reduces Size and power requirements over a
multiple ASIC solutions, as well as eliminates multiple expensive Non-recurring engineering cost
for each ASIC. This kind of parallel operation allows the data to be processed at the rate that is
fifteen to 20 times lower than the A/D rate.

6
In the implementation of High data rate digital demodulator design , “National semiconductor’s
make “ADC08D1500 high performance low power dual channel 8bit ,1.5 GSPS, with an Effective
number of bits (ENOB) of 7.3 bits and a BER performance of 10-18
is used.
The main consideration for systems using the ADC08D1500 and Virtex-4 FPGA is the
signaling between the devices. There are two key issues when handling two channels (each
providing data at a rate of 1.5 billion(1.5 x 109) conversions per second) Signal integrity between
the ADC and FPGA and the rate of data transfer for each clock cycle. The ADC08D1500 uses low
voltage differential signaling (LVDS) for each of its data outputs and clock signal. The main
advantage of the LVDS signaling method is that you can achieve high data rates with a very low
power budget. Two wires are used for each discrete signal that is to be carried across the circuit
board, which should be designed to have a characteristic impedance of 100 Ohms (defined by the
LVDS standard). These traces are differentially terminated at the receiver with a 100 Ohm resistor
to match the transmission line. TheADC08D1500 has a total of four 8-bit data buses, plus a clock
and over-range signal that require an LVDS type connection to the FPGA(see Figure 2) .This adds
up to a total of 34 differential pairs, all of which require 100 Ohm termination.
The Virtex-4 device offers active digitally controlled impedance (DCI) and a simple passive
100 Ohm termination on chip within the I/O buffers of the device.
These on-chip termination methods eliminate the need to place passive resistors on the circuit board
and simplify the routing on the PCB.
The ADC08D1500 provides a de-multiplexed data output for each of its two channels.
Instead of providing a single 8-bit bus running at a data rate equal to the sampling speed, the ADC
outputs two consecutive samples simultaneously on two 8-bit data buses (1:2 de-mux)The converter
output has 1 : 2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each
bus to one half the sampling rate.
The ADC performance specifications are generally characterized in two ways namely, the
DC accuracy and dynamic performance.
The dynamic performance is more critical parameter for this application.
Dynamic performance includes measure of signal to noise ratio and harmonic distortion.
One of the fundamental measures in ADC measurement is the quantization error. Maximum
quantization error is determined by the resolution of the measurement. This may appear as noise
floor in FFT plot. For a given ADC resolution, the quantization noise limits the ADC to it’s
theoretical best SNR. The quantization noise can be reduced by selecting a higher resolution ADC
or by over sampling.
SNR (dB) = 6.02N + 1.76, where N is the resolution of ADC.
Limitations in the materials used in the fabrication of the ADCs will cause deviations from
the ideal transfer function response. These deviations define the DC accuracy and are characterized
by the dynamic performance specifications.
3. DESIGN OF COSTAS CARRIER RECOVERY LOOP
Carrier recovery is the process of extracting a coherent reference carrier from the received
modulated carrier signal. To correctly demodulate the data , a phase & frequency coherent carrier
is to be recovered and compared with the received signal in a product detector. To determine the
absolute phase of the received signal it is necessary to reproduce a carrier at the receiver that is in
phase & frequency coherence with the transmit reference oscillator. In the case of High data rate
QPSK modulated signal the carrier cannot simply be tracked with a standard Phase-lock loops
(PLL) at the receiver , but a more sophisticated method of carrier recovery is required . Phase-lock
loops (PLLs) have been one of the basic building blocks in modern communication systems. There
are many kinds of Phase Lock Loops: the Costas Loop or Quadrature loop , which is named by J.
P. Costas, a pioneer in synchronous communications, is a very good choice for the high data rate

7
digital demodulator design. The implementation is very powerful and useful in many situations.
Further we can precisely determine and correct the Doppler variations.
The Costas or the quadrature loop involves two parallel tracking loops operating simultaneously
from the same VCO. (Ref fig.5)
One loop called the in-phase loop uses the VCO directly for tracking .The other loop uses 90
degrees shifted VCO .The mixer outputs are multiplied, filtered and used to control the VCO. The
low pass filters in each arm must be wide enough to pass the carrier modulation without distortion.
The in-phase mixer generates the cosine terms. The quadrature mixer generates the sine terms.
The multiplier output
I(t) . Q(t) = A2 . m2 (t) . sinΨe . cosΨe
= A2/2 . 2.sinΨe(t).
o Where Ψe = phase error.
The double frequency terms are eliminated by the Low pass filters following the
multiplication. An error signal is generated by multiplying the two outputs of the Low pass filters.
The error signal is filtered by the Loop filter ,whose output is the control voltage which drives the
VCO . The Costas loop thus tracks the phase variations with VCO without interference from the
carrier modulation.
The limiter cross over arms are used for controlling the amplitude variations and regulate the
CNR within the loop . At high SNR the limiter output will have sign that is identical to the present
data bit polarity.
The optimum Low pass filter for rejecting the double frequency term in the Costas loop is a
filter matched to the information bearing data signal. If matched filters are used for the Low pass
filters , their outputs can be sampled and directly used for Bit synchronization.
The output of the VCO contains a phase ambiguity of Π/4 radians, which can be overcome
by differential encoding of the data at the transmitter and differential decoding after demodulation
at the receiver.
The loop filter bandwidth and the arm filter bandwidths are the critical tasks to be addressed
for designing the demodulator to cater to multimission data reception application.
The fundamental expression that relates the mean squared phase jitter in the phase lock loop
to the SNR in the loop is
σφ
2
= 1/ρ rads2
,Where ρ= SNR in the loop.
σφ
2
= (BL / Bi ) *[ 1/ (S/N)i]
Where (S/N)i is the input Signal-to –Noise ratio
BL = One sided loop Bandwidth
Bi = One sided IF bandwidth (Arm filter bandwidth)
If SL is the squaring loss in the carrier regeneration process,
σφ
2
= 1/ρL SL Where ρL = Loop SNR
The term squaring loss is used to describe the degradation in the loop SNR due to SXN and NXN
distortions occurring the arm filters . The squaring loss depends on the shape of the input pre-filter,
the data waveform and the Eb/No.
SL = h1 + h2 Tb /α
α 2 Eb/No
Where Tb = Bit duration
α = Bif / Rs

8
Bif = Double sided IF bandwidth
Rs = Data rate
-∞
h1 = 1/2π ∫ Sm (ω ) l Hc (ω )l4
dω
∞
-∞
h2 = 1/2π ∫ l Hc (ω )l4
dω
∞
Where Hc (ω ) = Low pass equivalent of the input band pass filter transfer function.
Sm (ω ) = Spectrum of the modulated signal.
It is seen from the above relation that if the input pre-filter band width is too wide relative to the bit
duration 1/Tb ,h1 and h2 will increase ,while if it is too narrow , α decreases and both of these
increase the squaring loss. QPSK requires much higher S/N ratio in the XPLL than that required for
BPSK for a given bit error rate performance.
Figure 5 Costas Loop Diagram
The analysis substantiated with the practical results indicate that the double sided loop band
width of 30 KHz for the Costas PLL is adequate for QPSK operation up to the Symbol rates of
about 160 MBPS. For lower data rates ( < 10 MBPS ) the loop bandwidth has to be narrowed for
better SNR . The Pre-filter band width has to be designed as equivalent to 55% of the highest baud
rate expected.
The Digital implementation of the basic Costas loop for High data rate QPSK demodulator is
proposed to be carried out on a Single FPGA (Xilinx Vertex-4 or Spartan-3E Chips.)
An average high-density design of up to 100,000 gates can be compiled in less than 30
minutes thus giving more time to make analysis for perfect design.
The Digital Costas loop (DCL) has four basic components: a phase detector, numerically controlled
oscillator (NCO), digital low pass FIR and a loop filter. A second order FIR Low pass filter and 2nd
order loop filter are adequate to track the Doppler shift variations with good performance.
3.1 Digital Implementation of Costas blocks
Phase Detector: It compares the phase difference between synthesized output frequency and
reference input. Commonly used XOR gate or edge sensitive phase detector can be selected. The
function of the phase detector is to generate an error signal, which is used to return the oscillator
frequency whenever its output deviates from a reference input signal.

9
Figure 6 Block Diagram of Realized Phase Detector
3.1Digital low pass FIR filter: Mixed signal has to be filtered to isolate the portion of the spectrum
containing the signal of interest. The filter typically has to be a narrow-band filter with a fairly high
rejection of unwanted spectrum. This is to done at a much lower sample rate using a less
computationally intensive filter.
Calculation Of Coefficients:
Enter the pass band ripple : 0.5 dB
Enter the stop band ripple : 30 dB
Enter the pass band edge freq : 28000000 Hz
Enter the stop band edge freq : 44000000 Hz
Enter the sampling freq : 157500000 Hz
-0.0536, -0.0365, +0.1693, +0.4046, +0.4046, +0.1693, -0.0365, -0.0536
This FIR filter is implemented in FPGA using VHDL simulation on Xilinx development tools. The
Basic design Parameters of FIR filter are
Fully configurable fixed point FIR filter.
Two's complement arithmetic.
Pipeline architecture.
Parametric filter order (no. of taps), data and coefficient width.
Configurable output precision.
Coefficients stored in internal ROM
4. HARDWARE TEST RESULTS
Simulate filter impulse response in VHDL simulation tool Synthesize filter using VHDL
synthesis tool. Place-and-route using Xilinx place-and-route tools -circuit clock speed is output by this
tool -circuit area is determined by the number of slices/CLBs used.

10
4.1 QPSK Costas loop implementation Results
A system-level design was developed that modeled a simple transmitter and channel that simulated a
QPSK modulated Signal for a data rate of 52.5 MB.
Figure 7 Modulation constellation diagram.
Figure 8 Eye diagram Transmitter diagram.
Figure 9 Rotating Constellation diagram
Figure 10 Eye diagram of receiver

11
Figure 11 Input and Output Phase Slopes
Figure 12 Phase error and De-rotated Constellation
4.2 FPGA Implementation
Device family selected : Spartan -3E series Xilinx FPGAs. Arithmetic realization of the QPSK
Costas loop : Matlab and Simulink After the quantized model was verified in the Simulink
domain, a conventional FPGA implementation flow, using VHDL is used to produce the final
design.
4.3 Hardware
Digital PCB (Base Board) having
1-2 FPGAs to do Carrier recovery & Bit synchronization
High speed digital parallel interface (external Dual ADCs)
Input/output Connectors (IF input, multiplex and non-multiplex. I and Q Bit Streams)
RS-232 D-M console configuration port
12 V/5.0 V DC power Head.
Reference clock 10MHz 0dBm (temperature compensated,
ADC08D1500 A/D PCB modules
Display module PCB has
Display, Keypad.
Power supply module
12/5 V output or 230 V +/- 10% AC input.
Base mounting plate and box

12
6. CONCLUSION
The primary objective of the design is to develop a fully programmable high data rate digital
demodulator using VLSI techniques and devices. The high data rate digital demodulator has the
capability to demodulate any QPSK signal with a data rate ranging from 10 MBPS to 320 MBPS.
The design concepts and implementation aspects of a Costas Loop Carrier recovery have been given
more emphasis, which have been elaborately discussed in this paper. The Simulations are carried
out for a nominal QPSK signal with a data rate of 105 MBPS (52.5 X 2). Further the process of
implementing the Digital Costas Loop (DCL) on an FPGA has also been thoroughly discussed. The
Costas Loop design is tested extensively in MATLAB for design validation and performance
optimizations as required for high data rate applications. The simulation and implementation
results show that this whole architecture results in robust and accurate carrier recovery. The Digital
Low Pass FIR filter optimizations thereby make it feasible to implement an entire Costas Loop on
FPGA, with a BER performance close to the theoretical curve and with an implementation
margin < 2 dB.
7. REFERENCES
(1) K. Feher, “Wireless Digital Communications”, Prentice Hall.
(2) D. Pleasant, “Practical Simulation of Bit Error Rates”, Appl. Microwaves & Wireless,
Winter94.
(3) E. Franke & J. Wunderlich, Practical BER Measurements.” Paper- R.F. Expo, West, Jan 1995.
(4) A.B. Carlson, “ Communications Systems”, McGraw Hill
(5) J.C. Bellamy, “Digital telephony”, John Wiley, 1982.
(6) H.R. Walker, “ Modulation Analysis” Vol 13, Encyclopedia of Electrical and Electronic
Engineering, John Wiley -also Applied Microwaves and Wireless magazine, July/Aug 1997
(7) Mischa Schwartz, “Information Transmission, Modulation and Noise.”
McGraw Hill. 1959.
(8) Proakis and Saleh, “ Communications System Engineering” Prentice Hall, 1994.
(9) K. Feher, "Telecommunications Measurements, Analysis, and Instrumentation", Noble
Publishing, Atlanta, Ga.
(10) R. E. Best, "Phase Locked Loops" McGraw Hill.
(11) Taub and Schilling, "Principals of Communications Systems" McGraw Hill.
(12) Horan, S., Introduction to PCM Telemetering Systems, CRC Press, Boca Raton, FL, 1993,
ISBN 0-8493-4208-2.
(13) Feher, K., Telecommunications Measurements, Analysis, And Instrumentation, Prentice-Hall
Press, Englewood Cliffs, NJ, 1987, ISBN 0-13-902404-2.
(14) CCITT Rec. 0151, Yellow Book, Vol. 4 Fascicle IV.4 Recommendation 0.151.
(15) Shashank Bholane and Devendrasingh Thakore, “Sender To Receiver Synchronization In
Wireless Sensor Networks – A Simulation Study” International journal of Computer Engineering &
Technology (IJCET), Volume 3, Issue 2, 2012, pp. 265 - 270, ISSN Print: 0976 – 6367,
ISSN Online: 0976 – 6375.
(16) T.Regu and Dr.G.Kalivarathan, “Prediction of Wireless Communication Systems in the
Context of Modeling”, International journal of Electronics and Communication Engineering
&Technology (IJECET), Volume 4, Issue 1, 2013, pp. 11 - 17, ISSN Print: 0976-6464,
ISSN Online: 0976-6472.
(17) T.Regu and Dr.G.Kalivarathan, “Prediction of a Reliable Code for Wireless Communication
Systems”, International Journal of Electrical Engineering & Technology (IJEET), Volume 4,
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