Fundamentals of All-Digital Phase Lock Loop Used in Digital Radio Processor

1. All-Digital Phase Lock Loop Imran Bashir “The Lab Guy” March 10 th , 2009

3. All-Digital PLL (ADPLL) References [1], [3] - Bogdan Staszewski, John Wallberg 1 3 4 2 ADPLL operates in phase domain.

5. Digitally-Controlled Oscillator Core The C-V curve of the MOS can have a large linear range which is function of the DCO swing.

8. DCO ΣΔ : Design Considerations Composite ΣΔ Noise ↑, N ↑ , M ↓ , TB size ↑, f CLK ↓ Critical parameters: M, CLK, N, δ C -> Δ f Due to resolution of digital input (M) Due to size of capacitor Δ f Reference [3] - Bogdan Staszewski, Chih-Ming Hung

9. DCO ΣΔ : Design Considerations Effect of SD order (N) M = 10, Δ f = 30kHz, f CLK = 450MHz N = 1 N = 2 N ↑ , L SD,M Х , L SD, Δ f lower between 1-10M & higher @ 100MHz Composite response (solid black line) DOES NOT include natural DCO phase noise!

10. DCO ΣΔ : Design Considerations Effect of Fractional Word Length (M) N = 2, Δ f = 30kHz, f CLK = 450MHz M = 2 M = 10 Composite response (solid black line) DOES NOT include natural DCO phase noise! M ↑ , L SD,M ↑ , L SD, Δ f X, Current consumption ↑

11. DCO ΣΔ : Design Considerations Effect of Capacitor Size ( Δ f) M = 10, N = 2, f CLK = 450MHz Δ f = 10kHz Δ f = 30kHz Δ f ↑ , L SD,M ↑ , L SD, Δ f ↑ Composite response (solid black line) DOES NOT include natural DCO phase noise!

12. DCO ΣΔ : Design Considerations Effect of ΣΔ Clock ( f CLK ) M = 10, N = 2, Δ f = 30kHz f CLK = 225MHz f CLK = 450MHz f CLK ↑ , L SD,M X , L SD, Δ f ↑ Composite response (solid black line) DOES NOT include natural DCO phase noise!

14. Phase Detector CKR = Re-timed FREF CKV = DCO clock

15. Phase Detector Integer Error Correction Reference [6] - Bogdan Staszewski Φ = 3 Φ = 0 Modulo-16 N = 10 Error Resolution of Integer Correction = ±0.5 · DCO Cycle

17. Time-to-digital Converter (TDC)

18. Time-to-digital Converter (TDC)

20. TDC: Important Concepts Effect of DCO Frequency ADPLL Frequency ↓ # of Inverters ↑ Current consumption ↑

21. TDC: Important Concepts Effect of Inverter Delay Δ t inv ↓ TDC Quantization Noise ↓ # of Inverters (L) ↑ Current consumption ↑

24. Noise Modeling in ADPLL References [1], [3] - Bogdan Staszewski, John Wallberg Loop parameters  1-4

27. Noise Modeling in ADPLL Tip: When even debugging spur source, study the effect of loop bandwidth on spur level. FREF harmonic spur Blue Trace = Yellow Trace = DCO Supply spur Blue Trace = Yellow Trace = Wide Loop Narrow Loop Wide Loop Narrow Loop

32. Tuning the ADPLL: Step 2 -119dBc/Hz -119dBc/Hz PN @ 400kHz - 64-kHz 0-dB CL BW - 13.7dB Gain Margin 0.9 ° 1.1 ° PTE - -36dB CL gain @ 400kHz -67dB -67.5dB MODSPEC @ 400kHz - 44 ° Phase Margin Measured Simulated Parameter 0.1 ° -74 DCXO 1.1 ° -49.7 Composite 1.1 ° -50 DCO 0.3 ° -62 TDC RMS PE dB Noise Source

49. DCO Pulling: Solution α =7, ρ =16, λ =0x3555 Loop Bandwidth = 64-kHz Phase margin = 44 ˚ Gain margin = 13.7 dB α =5, ρ =14, λ =0x2334 Loop Bandwidth = 233-kHz Phase margin = 49 ˚ Gain margin = 11.1 dB Dynamic adjustment of ADPLL bandwidth between 64-kHz and 233-kHz.

50. DCO Pulling: Measurement Results

55. DCO Gain Calibration & Compensation 40% Variation over Process & 15% Variation over Temperature

56. DCO Gain Calibration & Compensation

57. DCO Gain Calibration & Compensation Without calibration and compensation, the phase error of the transmitter will fail 3GPP GSM specification. GSM 3GPP limit (5 degrees) Measured Simulated Target specification (3 degrees)

58. DCO Gain Calibration & Compensation Data Packet DCO Gain Estimation

60. TDC Calibration & Compensation Error needs to be within ±2% to meet 3  RMS phase-error spec.

62. Calibration of DCO Current Variation of DCO Phase Noise Operating beyond optimum bias setting effects the DCO reliability. 400kHz Offset

64. Calibration of DCO Current Validation of Proposed Solution Optimum DCO current using PHE based estimation PHE based estimation of DCO noise correlates with the measured DCO integrated noise.

66. DCO Frequency Calibration & Compensation The allocated time for ADPLL lock may not be adequate given DCO center frequency variation.

69. Noisy/Defective vs. Normal DCO PTE is determined based on PHE based estimation of DCO noise. References [5] - Oren Eliezer, Imran Bashir

70. Block Diagram for Cap. Test DCO phase capacitor toggling time domain PHE waveform H(S) References [5] - Oren Eliezer, Imran Bashir