2.5D? 3D? What? Overview of 3D Integrated Circuit Packaging and Test Challenges presented at Silicon Valley Test Workshop (November 11, 2011) by Ira Feldman (www.hightechbizdev.com)

1. Feldman Engineering
2.5D? 3D? What?
Overview of 3D Integrated Circuit Packaging and Test Challenges
Ira Feldman
November 11, 2011
© 2011 Feldman Engineering Corp.
www.feldmanengineering.com Silicon Valley Test Workshop 2011

2. Outline
Silicon Valley Test Workshop 2011
} Why 2.5D & 3D ICs?
} Building stacks
} TSV Processes
} 2.5D & 3D stacks
} Process & Test Flows
} Wafer Probe Solutions
} Key Organizations &
Activities
} Future?
2

3. Silicon Valley Test Workshop 2011
Disclaimer – This is the “new
frontier” and things will change… 3

4. Package Proliferation
Silicon Valley Test Workshop 2011
“Backend to the Front Line” William Chen, ASE Group, SWTW 2011 4

5. Very low power & high density (small volume)
Silicon Valley Test Workshop 2011
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Flickr - blakespot

6. Silicon Valley Test Workshop 2011
15x performance
90% less space
70% less power per bit*
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* Micron – Hybrid Memory Cube

7. Outline
Silicon Valley Test Workshop 2011
} Why 2.5D & 3D ICs?
} Building stacks
} TSV Processes
} 2.5D & 3D stacks
} Process & Test Flows
} Wafer Probe Solutions
} Key Organizations & Activities
} Future?
7

8. “Stacking 1.0”
Silicon Valley Test Workshop 2011
Toshiba’s 64 GB Embedded NAND Flash Module
December 2009 8

9. TSV Processing
3D TSV via integration MAIN scenarios
Silicon Valley Test Workshop 2011
Step #1 Step #2 Step #3 Step #4 Step #5 Step #6
BEOL 450°C Thinning + De-Bonding
Via TSV Etch TSV Fill FEOL 1000°C Backside prep
First
 Vias are
made before
CMOS
Handling carrier
Thinning +
Via FEOL 1000°C TSV Etch TSV Fill BEOL 450°C Backside prep
De-Bonding
Middle
 Vias are
made between
CMOS and
Handling carrier
BEOL
TSV Fill +
Via
BEOL 450°C Thinning De-Bonding
FEOL 1000°C TSV Etch Backside prep
Last
 Vias are
made after
BEOL
Handling carrier Handling carrier Handling carrier
TSV Etch TSV Fill +
FEOL 1000°C Bonding Thinning
Via After +
Backside prep
Bonding BEOL 450°C
Vias are
made after
Bonding
(C2W or W2W)
Courtesy of Yole Developpement 9
© 2009 • 21
Copyrights © Yole Développement SARL. All rights reserved.

10. 3D integration process options using TSV
 TSV process flow
Silicon Valley Test Workshop 2011
Siウェハ
FEOL BEOL
Assembly / Packaging
(transistors) (metal layers)
TSV
process
(1) Via-first (2) Via-middle (3) Via-last
 TSV interconnect methods KGD: known good die
(1) C2C: chip-to-chip (2) C2W: chip-to-wafer (3) W2W: wafer-to-wafer
Pros Flexible Flexible High throughput
Use of KGD Use of KGD
Cons Handling, Bonding Handling, Bonding Same chip size, Yield
“Panel Discussion: Advanced Packaging and 3D Technologies”, Kenichi Osada, Hitachi,
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16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011

11. Silicon Valley Test Workshop 2011
“Wafer Probing on Fine-Pitch Micro-Bumps for 2.5D- and 3D-SICs”, Erik Jan Marinissen (IMEC), Peter Hanaway (Cascade Microtech), et. al.
11

12. Hybrid Memory Cube - Micron
Silicon Valley Test Workshop 2011
Justin Rattner (Intel CTO) Keynote @ IDF 2011 12

13. Process Flow & Test Coverage
TODAY
Silicon Valley Test Workshop 2011
Wafer Test Final Test Board Test System Test
Parametric
Thin
Die Place
Singulate Packaged Board/
Fabricate (on Part Solder / Module Integrate System
wafer) Bond / Flip Chip Attach
Seal
Fab Process Fab & Post Process PCA Process Integration Process
Functionality Functionality Functionality Functionality
Partial to full speed At full speed
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14. Known Good Die - Flow & Test Coverage
TODAY
Silicon Valley Test Workshop 2011
Wafer Test* Board Test System Test
Parametric
Burn-In
Die Place
Thin Board/
Fabricate (on KGD Solder / Module Integrate System
wafer) Singulate Attach
Additional QA
Fab Process PCA Process Integration Process
Functionality Functionality Functionality
At full speed
* Predominant path to KGD is via wafer based testing. There are some solutions for die based socket testing such as Aehr Test’s DiePak.
14

15. Stacked Die – KGD (singulated)
Silicon Valley Test Workshop 2011
Stack Test ??? Board Test System Test
KGD
1
…
Place
Die Board/
Stack Solder / Integrate System
Stack Module
Attach
KGD
n Stack Process PCA Process Integration Process
Functionality ??? Functionality Functionality
At full speed???
15

16. Stacked Die – NKBD (wafers)
Wafers or reconstituted wafers of Not Known Bad Die:
• Thinned
Silicon Valley Test Workshop 2011
• Partial to full speed tested
Wafer Test ??? Stack Test ??? Board Test System Test
Wafer
1
…
Place
Stack
Wafer Singulate
Die Board/ Integrate System
Solder / Module
Stack Stack Attach
Wafer
n Stack Process Dice Process PCA Process Integration Process
Functionality
Functionality ??? Functionality ??? Functionality
At full speed??? At full speed???
16

17. Stacked Die – Sub Stacks (wafers)
Silicon Valley Test Workshop 2011
Memory Stack Test
Wafer @ Memory Vendor
… 1
Stack Memory
Stack
Full Stack Test
@ Integrator ???
Wafer
n
Stack Memory
Stack
CPU
CPU
Wafer
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18. Silicon Valley Test Workshop 2011
“3D TSV Program Overview – Presented to GSA Oct 20, 2011” Sitaram Arkalgud, SEMATECH
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19. Scan Testing
} Provide access and control to cores at all test steps
Silicon Valley Test Workshop 2011
} If proper infrastructure (P1838) & connectivity is present
} Does not replace full access to all “pads” for KGD.
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20. Outline
Silicon Valley Test Workshop 2011
} Why 2.5D & 3D ICs?
} Building stacks
} TSV Processes
} 2.5D & 3D stacks
} Process & Test Flows
} Wafer Probe Solutions
} Key Organizations & Activities
} Future?
20

21. ISSCC 2011 PAP
Mobile DRAM predecessor to Wide I/O
Silicon Valley Test Workshop 2011
28.5.1: Chip architecture of 1Gb > 1000 micro-bumps image of
FigureAl pads (muxed) to Wide-I/O DRAM and SEM
microbumps.
test with existing 50 µm pitch array Figure 28.5.2: Block and timing diagr
probe technology
Figure 28.5.7: Photograph of
“A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4×128 I/Os Using TSV-
Based Stacking” Jung-Sik Kim, et.al., Samsung Electronics, ISSCC 2011
fabricated chip with microbumps and vertical section
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2-stacked Wide-I/O DRAMs.

22. Electroplated Micro-Bump Bonding
Silicon Valley Test Workshop 2011
• Cylindrical bumps
Side1: Cu (5 µm )
Side2: CuSn (5 µm + 3.5 µm)
• Size (today)
Diameter : 25 µm
Pitch : 40 µm
Scaling down…
Courtesy of Cascade Microtech & IMEC
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23. FormFactor: NanoPierce™ Contact Solution
FormFactor NanoPierce Contact
Silicon Valley Test Workshop 2011
Contact Surface for NanoPierce™ Contact
40umx50um Array
FormFactor Proprietary NanoPierce™ Contacts are Highly Scalable
Metal “NanoFiber”
contact element
Thousands Easily Fabricated at Very Dense Pitch
15um
11
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“Challenges and Solutions for Testing of TSV and MicroBump Devices by Direct Connection”, Ben Eldridge, 3D Test Workshop 2011
Metal NanoFiber Contacts With Many Contact Points in
15 Micron Square

24. Touchdown Technologies: Metal MEMS Probes
Silicon Valley Test Workshop 2011
“A Low-Force MEMS Probe Solution For Fine-
Pitch 3D-SIC Wafer Test”, Matthew W. Losey, Probe beam: ~10 µm W x 80 µm L
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et. al., 3D Test Workshop 2011 100 µm

25. Cascade Microtech: Lithographically Printed
100 µm pitch 35 µm pitch
~1 gF/tip
Silicon Valley Test Workshop 2011
~10 gF/tip
Scale by K
XYZ/K
Force/K2
Fully-routed 6 x 50 array at 40 x 50 µm pitch
New space transformer technology
“Probing Strategies for Through-Silicon Stacking”,
Eric Strid, et. al, 3D Test Workshop 2011 25

26. Outline
Silicon Valley Test Workshop 2011
} Why 2.5D & 3D ICs?
} Building stacks
} TSV Processes
} 2.5D & 3D stacks
} Process & Test Flows
} Wafer Probe Solutions
} Key Organizations & Activities
} Future?
26

27. Silicon Valley Test Workshop 2011
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“3D IC Technology’s Promise for Communications and Storage ICs”, Brian D. Gerson, PMC-Sierra, GSA 4/28/11

28. Organizations & Programs
Silicon Valley Test Workshop 2011
} IEEE P1838 - Standard for Test Access Architecture for Three-
Dimensional Stacked Integrated Circuits
standards.ieee.org/develop/project/1838.html
} Semi wiki.sematech.org/3D-Standards
} Sematech – 3D Program www.sematech.org/research/3D
} Unit Process, Module Development, Enablement Center
} Global Semiconductor Alliance – 3D-IC Working Group
www.gsaglobal.org/3dic
} JEDEC – Wide I/O www.jedec.org
} IMEC www2.imec.be
} Industrial Technology Research Institute (ITRI) www.itri.org.tw
} A*Star Institute of Microelectronics www.ime.a-star.edu.sg
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29. Recent Conferences
Silicon Valley Test Workshop 2011
} GSA Memory Conference (Mar ‘11)
www.gsaglobal.org/events/2011/0331/program.aspx
} IEEE Semiconductor Wafer Test Workshop (June ‘11 & ‘12)
www.swtest.org
} ATE Vision 2020 (w/Semicon West – Jul ‘11)
www.atevision.com
} Semicon Taiwan – SiP Global Summit 2011(Sep ‘11)
} 3D IC Test Forum semicontaiwan.org/en/node/1566
} 3D IC Technology Forum semicontaiwan.org/en/node/1571
} IEEE International Workshop on Testing Three-Dimensional
Stacked Integrated Circuits (w/ITC – Sep ’11 / Nov ‘12)
3dtest.tttc-events.org
} MEPTEC 2.5D, 3D and Beyond – Bringing 3D Integration to
the Packaging Mainstream (Nov 9, 11) www.meptec.org
} MEPTEC-Semi KGD in an Era of Multi-Die Packaging and 3D
Integration (Nov 10, 11) www.meptec.org
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30. Outline
Silicon Valley Test Workshop 2011
} Why 2.5D & 3D ICs?
} Building stacks
} TSV Processes
} 2.5D & 3D stacks
} Process & Test Flows
} Wafer Probe Solutions
} Key Organizations & Activities
} Future?
30

31. TBD - To Be Determined
Silicon Valley Test Workshop 2011
} Yield
} Preferred Via Process
} Singulate dies before or after
stacking
} Wafer probe and handling of
die stacks on wafer or
singulated stacks
} Business models – who is
responsible for what
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32. Future
Silicon Valley Test Workshop 2011
} Hard work – getting it to
work!
} Increased test complexity
earlier in process
} Shrinks – especially micro-
bumps and pitch
Profits or Costs?
32

33. Thank You!
Silicon Valley Test Workshop 2011
Ira Feldman
ira@feldmanengineering.com
Visit my blog
www.hightechbizdev.com
for additional resources.
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34. Other References & Resources
Silicon Valley Test Workshop 2011
} Hybrid Memory Cube Consortium www.hybridmemorycube.org
} 3D-IC Alliance www.3d-ic.org (event & blogs/paper listing)
} Discussion groups / 3D news:
} www.3dincites.com
} www.3d-ics.com
} 3D-IC group on www.linkedin.com
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