VHdl lab report

HDL Lab Report
SUBMITTED BY AVINASH T(M130122EC) , JINESH K B(M130121EC)
jineshkb91@gmail.com

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Table of Contents 1
1. a D LATCH 2
b D FLIP FLOP 8
2.a JK FLIP FLOP 13
b. T FLIP FLOP 22
3. a 4X1 MULTIPLEXER IN STRUCTURAL MODEL 28
b. 4X1 MULTIPLEXER IN DATA FLOW MODEL 34
4. FULL ADDER 38
5. 2 TO 4 DECODER 46
6. SEVEN SEGMENT DISPLAY 50
7. 4X2 PRIORITY ENCODER 55
8. SYNCHRONOUS COUNTER 60
9. RING COUNTER 68
10. JHONSON COUNTER 75
11. SHIFT REGISTER 80
12. a SEQUENCE DETECTOR FOR 010 USING MOORE MECHINE 87
b SEQUENCE DETECTOR FOR 010 USING MEALY MECHINE 93
c SEQUENCE DETECTOR FOR 110 OR 0011 99
13. XS-3 TO BCD CONVERTER 108
14. TRAFFIC LIGHT CONTROLLER 114

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1.a D LATCH
AIM: To design a D latch using vhdl modelling.
THEORY:
D latch is similar to D flip flop except that it changes the output in the active high phase of input
clock(enable).
TRUTH TABLE:
D Q
0 0
1 1
SCHEMATIC DIAGRAM:
VHDL CODE:
-------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

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ENTITY D_LATCH IS
PORT ( D,CLOCK,PR,CLR : IN STD_LOGIC;
Q,QBAR : OUT STD_LOGIC);
END D_LATCH;
ARCHITECTURE BEHAVIORAL OF D_LATCH IS
SIGNAL S:STD_LOGIC;
BEGIN
PROCESS(CLOCK,PR,CLR,D)
BEGIN
IF(CLR='1' AND PR='0') THEN S<='0';
ELSIF(CLR='0' AND PR='1') THEN S<='1';
ELSIF(CLR='0' AND PR='0') THEN
IF(CLOCK='1') THEN S<=D;
END IF;
END IF;
END PROCESS;
Q<=S;
QBAR<= NOT S;
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;

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ENTITY TB_D_LATCH IS
END TB_D_LATCH;
ARCHITECTURE BEHAVIOR OF TB_D_LATCH IS
-- COMPONENT DECLARATION FOR THE UNIT UNDER TEST (UUT)
COMPONENT D_LATCH
PORT(
D : IN STD_LOGIC;
CLOCK : IN STD_LOGIC;
PR : IN STD_LOGIC;
CLR : IN STD_LOGIC;
Q : OUT STD_LOGIC;
QBAR : OUT STD_LOGIC
);
END COMPONENT;
--INPUTS
SIGNAL D : STD_LOGIC := '0';
SIGNAL CLOCK : STD_LOGIC := '0';
SIGNAL PR : STD_LOGIC := '0';
SIGNAL CLR : STD_LOGIC := '0';
--OUTPUTS
SIGNAL Q : STD_LOGIC;
SIGNAL QBAR : STD_LOGIC;

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-- CLOCK PERIOD DEFINITIONS
CONSTANT CLOCK_PERIOD : TIME := 10 NS;
BEGIN
-- INSTANTIATE THE UNIT UNDER TEST (UUT)
UUT: D_LATCH PORT MAP (
D => D,
CLOCK => CLOCK,
PR => PR,
CLR => CLR,
Q => Q,
QBAR => QBAR
);
-- CLOCK PROCESS DEFINITIONS
CLOCK_PROCESS :PROCESS
BEGIN
CLOCK <= '0';
WAIT FOR CLOCK_PERIOD/2;
CLOCK <= '1';
END PROCESS;
-- STIMULUS PROCESS
STIM_PROC: PROCESS
BEGIN
PR<='0','1' AFTER 5 NS,'0' AFTER 8 NS;

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CLR<='1','0' AFTER 3 NS;
D<='1','0' AFTER 10 NS,'1' AFTER 25 NS,'0' AFTER 27 NS,'1' AFTER
29 NS,'0' AFTER 31 NS,'1' AFTER 36 NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------
OUTPUT
RESULT
Implemented D-latch and verified its output.
SYNTHESIS REPORT
=======================================================================
* Final Report *
=======================================================================
Final Results
RTL Top Level Output File Name : D_latch.ngr
Top Level Output File Name : D_latch
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No

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Design Statistics
# IOs : 6
Cell Usage :
# BELS : 4
# INV : 1
# LUT2 : 3
# FlipFlops/Latches : 2
# LDCPE : 2
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 5
# IBUF : 3
# OBUF : 2
========================================================================
Device utilization summary:
Selected Device : 3s500efg320-4
Number of Slices: 2 out of 4656 0%
Number of 4 input LUTs: 4 out of 9312 0%
Number of IOs: 6
Number of bonded IOBs: 6 out of 232 2%
IOB Flip Flops: 2
Number of GCLKs: 1 out of 24 4%

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1.b D FLIP FLOP
AIM:
To design a D flip flop in vhdl using behavioural modelling.
THEORY:
The D ﬂip-ﬂop is widely used. It is also known as a "data" or "delay" flip-flop.The D flip-flop
captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of
the clock). That captured value becomes the Q output. At other times, the output Q does not change.
TRUTH TABLE:
D Q
0 0
1 1
SCHEMATIC DIAGRAM:
VHDL CODE:
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY D_FF IS

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PORT ( D,CLR,PR,CLOCK : IN STD_LOGIC;
END D_FF;
ARCHITECTURE BEHAVIORAL OF D_FF IS
SIGNAL S:STD_LOGIC:='0';
BEGIN
PROCESS(CLOCK,PR,CLR)
BEGIN
IF(CLOCK='1' AND CLOCK'EVENT) THEN S<=D;
END IF;
END IF;
END PROCESS;
Q<=S;
QBAR<= NOT S;
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_D_FF IS
END TB_D_FF;
ARCHITECTURE BEHAVIOR OF TB_D_FF IS
COMPONENT D_FF
PORT(
D : IN STD_LOGIC;
CLR : IN STD_LOGIC;
PR : IN STD_LOGIC;
Q : OUT STD_LOGIC;
);
END COMPONENT;
--INPUTS
SIGNAL D : STD_LOGIC := '0';

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--OUTPUTS
BEGIN
UUT: D_FF PORT MAP (
D => D,
CLR => CLR,
PR => PR,
CLOCK => CLOCK,
Q => Q,
QBAR => QBAR
);
BEGIN
CLOCK <= '0';
CLOCK <= '1';
END PROCESS;
-- STIMULUS PROCESS
STIM_PROC: PROCESS
BEGIN
D<='1','0' AFTER 10 NS,'1' AFTER 25 NS,'0' AFTER 40 NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------

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OUTPUT
RESULT
Implemented D flip and verified its output.
SYNTHESIS REPORT
========================================================================
* Final Report *
========================================================================
Final Results
RTL Top Level Output File Name : D_ff.ngr
Top Level Output File Name : D_ff
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 6
Cell Usage :
# BELS : 4
# INV : 1
# LUT2 : 3
# FDCPE : 2
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 5
# IBUF : 3
# OBUF : 2
========================================================================

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Number of IOs: 6
IOB Flip Flops: 2

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2.a JK FLIPFLOP
AIM:
To design a JK Flip flop in structural modelling.
THEORY:
The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R
= 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set
the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1
is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value.
JK flipflop can be made using a D flip flop by making D=J + Q
TRUTH TABLE
J K Q(t+1)
0 0 Q
0 1 0
1 0 1
1 1

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SCHEMATIC DIAGRAM:
VHDL CODE:
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY JK_FF IS
PORT ( J,K,PR,CLR,CLOCK : IN STD_LOGIC;
END JK_FF;
ARCHITECTURE BEHAVIORAL OF JK_FF IS
COMPONENT D_FF IS
END COMPONENT;

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COMPONENT AND_2 IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;
COMPONENT OR_2 IS
Y : OUT STD_LOGIC);
END COMPONENT;
SIGNAL S0,S1,S2,S3,S4,S5:STD_LOGIC:='0';
BEGIN
S1<=NOT K;
A0:AND_2 PORT MAP(J,S5,S0);
A1:AND_2 PORT MAP(S1,S4,S2);
A2:OR_2 PORT MAP(S0,S2,S3);
A3:D_FF PORT MAP(S3,CLR,PR,CLOCK,S4,S5);
Q<=S4;
QBAR<=S5;
END BEHAVIORAL;
-------------------------------------------------------------------

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TEST BENCH:
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_JK_FF IS
END TB_JK_FF;
ARCHITECTURE BEHAVIOR OF TB_JK_FF IS
COMPONENT JK_FF
PORT(
J : IN STD_LOGIC;
K : IN STD_LOGIC;
PR : IN STD_LOGIC;
CLR : IN STD_LOGIC;
Q : OUT STD_LOGIC;
);
END COMPONENT;
--INPUTS
SIGNAL J : STD_LOGIC := '0';
SIGNAL K : STD_LOGIC := '0';

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--OUTPUTS
BEGIN
UUT: JK_FF PORT MAP (
J => J,
K => K,
PR => PR,
CLR => CLR,
CLOCK => CLOCK,
Q => Q,
QBAR => QBAR
);
BEGIN
CLOCK <= '0';

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CLOCK <= '1';
END PROCESS;
-- STIMULUS PROCESS
STIM_PROC: PROCESS
BEGIN
J<='0','1' AFTER 15 NS,'0' AFTER 25 NS,'1' AFTER 31 NS,'0' AFTER
38 NS,'1' AFTER 42 NS;
K<='1','0' AFTER 10 NS,'1' AFTER 20 NS,'0' AFTER 30 NS,'1' AFTER
40 NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------
COMPONENTS USED
1.D Flip flop
LIBRARY IEEE;
ENTITY D_FF IS
END D_FF;
SIGNAL S:STD_LOGIC:='0';
BEGIN
PROCESS(CLOCK,PR,CLR)

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BEGIN
IF(CLOCK='1' AND CLOCK'EVENT) THEN S<=D;
END IF;
END IF;
END PROCESS;
Q<=S;
QBAR<= NOT S;
END BEHAVIORAL;
2. OR__2
LIBRARY IEEE;
ENTITY OR_GATE IS
PORT ( A : IN STD_LOGIC;
B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END OR_GATE;
ARCHITECTURE BEHAVIORAL OF OR_GATE IS
BEGIN
Y <= A OR B ;
END BEHAVIORAL;
3.AND_GATE
LIBRARY IEEE;
ENTITY AND_GATE IS
Y : OUT STD_LOGIC);
END AND_GATE;
ARCHITECTURE BEHAVIORAL OF AND_GATE IS
BEGIN
Y <= A AND B;
END BEHAVIORAL;

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OUTPUT
RESULT
Implemented JK flip flop in structural model and verified the output.
SYNTHESIS REPORT
========================================================================
* Final Report *
========================================================================
Final Results
RTL Top Level Output File Name : jk_ff.ngr
Top Level Output File Name : jk_ff
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 7
Cell Usage :
# BELS : 5
# INV : 1

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# LUT2 : 3
# LUT3 : 1
# FDCPE : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 6
# IBUF : 4
# OBUF : 2
========================================================================
Number of Slice Flip Flops: 1 out of 9312 0%
Number of IOs: 7

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2.b T FLIPFLOP
AIM:
To design a T flipflop in structural model.
THEORY:
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If
the T input is low, the flip-flop holds the previous value.
We can make a T flipflop from a JK flipflop by making J=K=T.
TRUTH TABLE:
T Q(t+1)
0 Q
1
SCHEMATIC DIAGRAM:

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VHDL CODE:
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY T_FF IS
PORT ( T,CLR,PR,CLOCK : IN STD_LOGIC;
END T_FF;
ARCHITECTURE BEHAVIORAL OF T_FF IS
COMPONENT JK_FF IS
PORT ( J,K,PR,CLR,CLOCK : IN STD_LOGIC;
END COMPONENT;
BEGIN
A0:JK_FF PORT MAP(T,T,PR,CLR,CLOCK,Q,QBAR);
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH:
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_T_FF IS

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END TB_T_FF;
ARCHITECTURE BEHAVIOR OF TB_T_FF IS
COMPONENT T_FF
PORT(
T : IN STD_LOGIC;
CLR : IN STD_LOGIC;
PR : IN STD_LOGIC;
Q : OUT STD_LOGIC;
);
END COMPONENT;
--INPUTS
SIGNAL T : STD_LOGIC := '0';
--OUTPUTS

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BEGIN
UUT: T_FF PORT MAP (
T => T,
CLR => CLR,
PR => PR,
CLOCK => CLOCK,
Q => Q,
QBAR => QBAR
);
BEGIN
CLOCK <= '0';
CLOCK <= '1';
END PROCESS;
-- STIMULUS PROCESS
STIM_PROC: PROCESS
BEGIN
PR<='1','0' AFTER 4 NS;

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CLR<='0','1' AFTER 6 NS,'0' AFTER 8 NS;
T<='0','1' AFTER 15 NS,'0' AFTER 27 NS,'1' AFTER 39 NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------
OUTPUT:
SYNTHESIS REPORT:
========================================================================
* Final Report *
========================================================================
Final Results
RTL Top Level Output File Name : t_ff.ngr
Top Level Output File Name : t_ff
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 6

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Cell Usage :
# BELS : 5
# INV : 1
# LUT2 : 4
# FDCPE : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 5
# IBUF : 3
# OBUF : 2
========================================================================
Number of IOs: 6

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3.a 4X1 MULTIPLEXER IN STRUCTURAL MODEL
AIM
To implement a 4X1 multiplexer in structural model.
THEORY
Here, the 4 X 1 multiplexer is designed using three 2 X 1 multiplexers. The lowest bit is
taken as the select line of two multiplexers and the outputs of these (s1 and s2) connected to the
input of next multiplexer. The highest bit, which is the select line of last multiplexer, selects any
one of the signals s1, s2 and displayed as the output.
TRUTH TABLE
INPUT
SELECT LINE
S(1) S(0)
OUTPUT
O
I(3)-I(0)
00 I(0)
01 I(1)
10 I(2)
11 I(3)
SCHEMATIC DIAGRAM

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VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY MUX_4X1 IS
PORT( I : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
S : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
O : OUT STD_LOGIC);
END MUX_4X1;
ARCHITECTURE STRUCTURAL OF MUX_4X1 IS
COMPONENT MUX_2X1 IS
PORT ( I : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
S : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
SIGNAL TEMP:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL TEMP1,TEMP2,TEMP3:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
TEMP1<=I(1)&I(0);
TEMP2<=I(3)&I(2);
TEMP3<=TEMP(1)&TEMP(0);
A0 : COMPONENT MUX_2X1 PORT MAP(TEMP1,S(0),TEMP(0));
A1 : COMPONENT MUX_2X1 PORT MAP(TEMP2,S(0),TEMP(1));
A2 : COMPONENT MUX_2X1 PORT MAP(TEMP3,S(1),O);
END STRUCTURAL;

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TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_MUX IS
END TB_MUX;
ARCHITECTURE BEHAVIOR OF TB_MUX IS
COMPONENT MUX_4X1
PORT(
I : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
O : OUT STD_LOGIC );
END COMPONENT;
SIGNAL I : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL O : STD_LOGIC;
BEGIN
UUT: MUX_4X1 PORT MAP (
I => I,
S => S,
O => O );

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STIM_PROC: PROCESS
BEGIN
I<="0110","0000" AFTER 100 NS;
S<="00","01" AFTER 20 NS,"10" AFTER 40 NS,"11" AFTER 60
NS,"00" AFTER 80 NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------
COMPONENTS USED
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY MUX_2X1 IS
S : IN STD_LOGIC;
O : OUT STD_LOGIC);
END MUX_2X1;
ARCHITECTURE DATAFLOW OF MUX_2X1 IS
BEGIN
O <= I(0)WHEN S ='0' ELSE I(1);
END DATAFLOW;
-------------------------------------------------------------------

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OUTPUT
RESULT
Implemented 4X1 mux in structural model and verified the output.
SYNTHESIS REPORT
========================================================================
* Final Report *
========================================================================
Final Results
RTL Top Level Output File Name : mux_4X1.ngr
Top Level Output File Name : mux_4X1
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 7
Cell Usage :
# BELS : 3
# LUT3 : 2
# MUXF5 : 1
# IO Buffers : 7

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# IBUF : 6
# OBUF : 1
========================================================================
Number of IOs: 7

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3.b 4X1 MULTIPLEXER IN DATA FLOW MODEL
AIM
To implement a 4X1 multiplexer in data flow model.
THEORY
Here 4X1 mux consisit of 4 input lines and 2 select lines according to the select line input
corresponding input line is connected to the output. Its operation is described in the truth table below.
TRUTH TABLE
INPUT
SELECT LINE
S(1) S(0)
OUTPUT
O
I(3)-I(0)
00 I(0)
01 I(1)
10 I(2)
11 I(3)
SCHEMATIC DIAGRAM

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VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY MULTIPLEXER IS
S : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
O : OUT STD_LOGIC);
END MULTIPLEXER;
ARCHITECTURE DATAFLOW OF MULTIPLEXER IS
BEGIN
O <= I(0)WHEN S ="00" ELSE
I(1)WHEN S ="01" ELSE
I(2)WHEN S ="10" ELSE
I(3);
END DATAFLOW;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_MUX IS
END TB_MUX;

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ARCHITECTURE BEHAVIOR OF TB_MUX IS
COMPONENT MULTIPLEXER
PORT(
S : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
O : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL O : STD_LOGIC;
BEGIN
UUT: MULTIPLEXER PORT MAP (
I => I,
S => S,
O => O );
BEGIN
I<="0110","0000" AFTER 100 NS;
S<="00","01" AFTER 20 NS,"10" AFTER 40 NS,"11" AFTER 60
WAIT;
END PROCESS;
END;

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OUTPUT
RESULT
Iplemented 4X1 mux in data flow model and variefied the output.
SYNTHESIS REPORT
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : multiplexer.ngr
Top Level Output File Name : multiplexer
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 7
Cell Usage :
# BELS : 3
# LUT3 : 2
# MUXF5 : 1
# IO Buffers : 7
# IBUF : 6
# OBUF : 1
=========================================================================
Number of IOs: 7

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4.FULL ADDER
AIM
To design full adder using structural model.
THEORY
A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce
a SUM and a CARRY output.
SUM= A⊕ B ⊕ Cin
CARRY= A B +Cin B+Cin A
Here full adder is realised using two half adders and an OR gate.
TRUTH TABLE
INPUT OUTPUT
A B Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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SCHEMATIC DIAGRAM
VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY FULLADDER IS
PORT ( A,B,CIN : IN STD_LOGIC;
SUM,CARRY : OUT STD_LOGIC);
END FULLADDER;
ARCHITECTURE BEHAVIORAL OF FULLADDER IS
COMPONENT HALF_ADDER IS

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END COMPONENT;
COMPONENT ORGATE IS
Y : OUT STD_LOGIC);
END COMPONENT;
SIGNAL S1,S2,S3 :STD_LOGIC;
BEGIN
HA0 : COMPONENT HALF_ADDER PORT MAP(A,B,S1,S2);
HA1 : COMPONENT HALF_ADDER PORT MAP (S1,CIN,SUM,S3);
OR0 : COMPONENT ORGATE PORT MAP(S2,S3,CARRY);
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_FULLADDER IS
END TB_FULLADDER;
ARCHITECTURE BEHAVIOR OF TB_FULLADDER IS
COMPONENT FULLADDER
PORT( A : IN STD_LOGIC;
B : IN STD_LOGIC;
CIN : IN STD_LOGIC;
SUM : OUT STD_LOGIC;
CARRY : OUT STD_LOGIC );
END COMPONENT;
SIGNAL A : STD_LOGIC := '0';
SIGNAL B : STD_LOGIC := '0';
SIGNAL CIN : STD_LOGIC := '0';
SIGNAL SUM : STD_LOGIC;
SIGNAL CARRY : STD_LOGIC;
BEGIN
UUT: FULLADDER PORT MAP (
A => A,
B => B,

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CIN => CIN,
SUM => SUM,
CARRY => CARRY );
STIM_PROC: PROCESS
BEGIN
A<='0','1' AFTER 160 NS,'0' AFTER 320 NS;
B<='0','1' AFTER 80 NS,'0' AFTER 160 NS,'1' AFTER 240 NS,'0'
AFTER 320 NS;
CIN<='0','1' AFTER 40 NS,'0' AFTER 80 NS,'1' AFTER 120 NS,'0'
AFTER 160 NS,'1' AFTER 200
NS,'0' AFTER 240 NS,'1' AFTER 280NS,'0' AFTER 320 NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------
COMPONENTS USED
1. HALF_ADDER
LIBRARY IEEE;
ENTITY HALF_ADDER IS
END HALF_ADDER;
ARCHITECTURE BEHAVIORAL OF HALF_ADDER IS
COMPONENT AND_GATE IS
Y : OUT STD_LOGIC);
END COMPONENT;
COMPONENT XOR_GATE IS
Y : OUT STD_LOGIC);
END COMPONENT;
BEGIN
A0: XOR_GATE PORT MAP(A,B,SUM);
A1: AND_GATE PORT MAP (A,B,CARRY);

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END BEHAVIORAL;
2. OR_GATE
LIBRARY IEEE;
ENTITY OR_GATE IS
B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END OR_GATE;
BEGIN
Y <= A OR B ;
END BEHAVIORAL;
3. XOR_GATE
LIBRARY IEEE;
ENTITY XOR_GATE IS
Y : OUT STD_LOGIC);
END AND_GATE;
ARCHITECTURE BEHAVIORAL OF XOR_GATE IS
BEGIN
Y <= A XOR B;
END BEHAVIORAL;

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4. AND_GATE
LIBRARY IEEE;
ENTITY AND_GATE IS
Y : OUT STD_LOGIC);
END AND_GATE;
BEGIN
Y <= A AND B;
END BEHAVIORAL;
5. NOT_GATE
LIBRARY IEEE;
ENTITY NOTGATE IS
Y : OUT STD_LOGIC);
END NOTGATE;
ARCHITECTURE BEHAVIORAL OF NOTGATE IS
BEGIN
Y <= NOT A ;
END BEHAVIORAL;

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OUTPUT
RESULT
Implemented full adder in structural model and verified the outputs.
SYNTHESIS REPORT
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : FULLADDER.ngr
Top Level Output File Name : FULLADDER
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 5
Cell Usage :
# BELS : 2
# LUT3 : 2
# IO Buffers : 5
# IBUF : 3
# OBUF : 2
========================================================================

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Number of IOs: 5

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5. 2 TO 4 DECODER
AIM
To implement a 2 to 4 decoder using when else statement.
THEORY
Decoders are circuits that are used to convert one form of binary code into another form.
Here we designed a 2 to 4 decoder and the truth table is given below.The two input data is
decoded into four output lines.
TRUTH TABLE
ENABLE INPUT
A
OUTPUT
Y
1 00 0001
1 01 0010
1 10 0100
1 11 1000
0 XX 0000
SCHEMATIC DIAGRAM

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VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY DECODER2_4 IS
PORT ( A : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ENABLE : IN STD_LOGIC;
Y : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END DECODER2_4;
ARCHITECTURE DATAFLOW OF DECODER2_4 IS
BEGIN
Y<="0001" WHEN ENABLE='1' AND A="00" ELSE
"0010" WHEN ENABLE='1' AND A="01" ELSE
"0000";
END DATAFLOW;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_DECODER IS
END TB_DECODER;

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ARCHITECTURE BEHAVIOR OF TB_DECODER IS
COMPONENT DECODER2_4
PORT(
A : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
SIGNAL A : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL ENABLE : STD_LOGIC := '0';
SIGNAL Y : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
UUT: DECODER2_4 PORT MAP (
A => A,
ENABLE => ENABLE,
Y => Y );
STIM_PROC: PROCESS
BEGIN
ENABLE<='0','1' AFTER 20 NS,'0' AFTER 100 NS;
A<="00","01" AFTER 40 NS,"10" AFTER 60 NS,"11" AFTER 80
WAIT;
END PROCESS;
END;

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OUTPUT
RESULT
Implemented 2 to 4 decoder using when else and variefied the output.
SYNTHESIS REPORT
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : DECODER2_4.ngr
Top Level Output File Name : DECODER2_4
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 7
Cell Usage :
# BELS : 4
# LUT3 : 4
# IO Buffers : 7
# IBUF : 3
# OBUF : 4
=========================================================================
Number of IOs: 7

HDL Lab Report
50
6.SEVEN SEGMENT DISPLAY
AIM
To design a seven segment display using with select statement.
THEORY
There are seven segments forming a figure-of-eight pattern. Each segment consists of one
or more LEDs. The 1’s are placed in cells where the segments are to be excited and 0’s are placed
where no excitations are required.
TRUTH TABLE
BCD input Seven segment output
I(3) I(2) I(1) I(0) O(6) O(5) O(4) O(3) O(2) O(1) O(0)
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 0 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 0 0 1 1

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SCHEMATIC DIAGRAM
VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SEVENSEGDISPLAY IS
O : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END SEVENSEGDISPLAY;
ARCHITECTURE BEHAVIORAL OF SEVENSEGDISPLAY IS

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BEGIN
WITH I SELECT
O <= "1111110" WHEN "0000",
"0011000" WHEN "0001",
"0110111" WHEN "0010",
"0111101" WHEN "0011",
"1001001" WHEN "0100",
"1101101" WHEN "0101",
"1001111" WHEN "0110",
"0111000" WHEN "0111",
"0000000" WHEN "1111",
"1111111" WHEN "1000",
"1111001" WHEN OTHERS ;
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.NUMERIC_STD.ALL;
ENTITY TB_SSE IS
END TB_SSE;
ARCHITECTURE BEHAVIOR OF TB_SSE IS
COMPONENT SEVENSEGDISPLAY
PORT(

HDL Lab Report
53
O : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
END COMPONENT;
SIGNAL O : STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
UUT: SEVENSEGDISPLAY PORT MAP (
I => I,
O => O
);
WITH
STIM_PROC: PROCESS
BEGIN
I<="0000","0001" AFTER 20 NS,"0010" AFTER 40 NS,"0011" AFTER
60 NS,"0100" AFTER 80 NS,"0101" AFTER 100 NS,"0110" AFTER 120
NS,"0111" AFTER 140 NS,"1000" AFTER 160 NS,"1001" AFTER 180
NS,"1111" AFTER 200 NS;
WAIT;
END PROCESS;
END;
OUTPUT

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RESULT
Implemented seven segment display using with select and variefied the output.
SYNTHESIS REPORT
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : SEVENSEGDISPLAY.ngr
Top Level Output File Name : SEVENSEGDISPLAY
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 11
Cell Usage :
# BELS : 7
# LUT4 : 7
# IO Buffers : 11
# IBUF : 4
# OBUF : 7
=========================================================================
Number of IOs: 11

HDL Lab Report
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7. 4x2 PRIORITY ENCODER
AIM:
To design a priority encoder using ‘when else’ statement in vhdl.
THEORY:
Similar to ordinay encoder except that if two or more inputs are given at the same time, the
input having the highest priority will take precedence.
TRUTH TABLE:
I3 I2 I1 I0 Y1 Y0
0 0 0 0 X X
0 0 0 1 0 0
0 0 1 X 0 1
0 1 X X 1 0
1 X X X 1 1
SCHEMATIC DIAGRAM:

HDL Lab Report
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VHDL CODE:
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY PRIORITY_ENC IS
PORT ( ENABLE : IN STD_LOGIC;
I : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR (1 DOWNTO 0));
END PRIORITY_ENC;
ARCHITECTURE BEHAVIORAL OF PRIORITY_ENC IS
BEGIN
Y<="11" WHEN I(3)='1' AND ENABLE='1' ELSE
"10" WHEN I(2)='1' AND ENABLE='1' ELSE
"ZZ";
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH:
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_PRIORITY_ENC IS
END TB_PRIORITY_ENC;

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ARCHITECTURE BEHAVIOR OF TB_PRIORITY_ENC IS
COMPONENT PRIORITY_ENC
PORT(
Y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
--INPUTS
SIGNAL ENABLE : STD_LOGIC := '0';
--OUTPUTS
SIGNAL Y : STD_LOGIC_VECTOR(1 DOWNTO 0);
-- NO CLOCKS DETECTED IN PORT LIST. REPLACE <CLOCK> BELOW WITH
-- APPROPRIATE PORT NAME
BEGIN
UUT: PRIORITY_ENC PORT MAP (
ENABLE => ENABLE,
I => I,

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Y => Y );
STIM_PROC: PROCESS
BEGIN
ENABLE<='1','0' AFTER 20 NS,'1' AFTER 25 NS;
I<="0111","1000" AFTER 5 NS,"0101" AFTER 10 NS,"0001" AFTER 15
NS,"0000" AFTER 20 NS,"1111" AFTER 25 NS,"0010" AFTER 30 NS,"0011"
AFTER 35 NS,"0001" AFTER 40 NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------
OUTPUT
SYNTHESIS REPORT
========================================================================
* Final Report *
========================================================================
Final Results
RTL Top Level Output File Name : priority_enc.ngr
Top Level Output File Name : priority_enc
Output Format : NGC
Keep Hierarchy : No

HDL Lab Report
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Design Statistics
# IOs : 7
Cell Usage :
# BELS : 5
# INV : 1
# LUT3 : 1
# LUT4 : 2
# MUXF5 : 1
# IO Buffers : 7
# IBUF : 5
# OBUFT : 2
========================================================================
Number of IOs: 7

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8. SYNCHRONOUS COUNTER
AIM
To design a 4-bit synchronous counter using structural model.
THEORY
A 4 bit synchronous counter is designed using 4 T flip flops. This circuit consist of an input
mode to select whether up or down counter. .The design equation for up /down counters are
given by
T0 = 1
T1 =Q0.MODE + 0.
T2= Q0Q1.MODE+ 0 1
T3= Q0Q1Q2.MODE+ 0 1 2 .
When mode=1,it works as up counter.
Mode=0,it works as down counter.
To implement this in structural mode it requires 4 T flipflops , 5 AND gates,3 OR gates and 1
NOT gate.
SCHEMATIC DIAGRAM

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VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY SYN_UP_DOWN IS
PORT ( MODE,CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END SYN_UP_DOWN;
ARCHITECTURE BEHAVIORAL OF SYN_UP_DOWN IS
COMPONENT TFF PORT(T,CLK :IN STD_LOGIC;
Q,QBAR: OUT STD_LOGIC);
END COMPONENT;
COMPONENT NOTGATE IS
Y : OUT STD_LOGIC);

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END COMPONENT;
COMPONENT AND_GATE IS
Y : OUT STD_LOGIC);
END COMPONENT;
COMPONENT OR_GATE IS
Y : OUT STD_LOGIC);
END COMPONENT;
SIGNAL MODEBAR : STD_LOGIC;
SIGNAL S,N,M,U,D:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
N0 : NOTGATE PORT MAP(MODE,MODEBAR);
T0 : TFF PORT MAP('1',CLK,S(0),M(0));
T1 : TFF PORT MAP(N(0),CLK,S(1),M(1));
A0: AND_GATE PORT MAP(S(0),MODE,U(0));
A1: AND_GATE PORT MAP(U(0),S(1),U(1));
A2: AND_GATE PORT MAP (S(2),U(1),U(2));
A3: AND_GATE PORT MAP(MODEBAR,M(0),D(0));
A4: AND_GATE PORT MAP(D(0),M(1),D(1));
A5: AND_GATE PORT MAP (M(2),D(1),D(2));
O0:OR_GATE PORT MAP(D(0),U(0),N(0));
Q<=S;
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_UP_DOWN IS
END TB_ UP_DOWN;

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ARCHITECTURE BEHAVIOR OF TB_ UP_DOWN IS
COMPONENT SYN_UP_DOWN
PORT(
MODE : IN STD_LOGIC;
CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
SIGNAL MODE : STD_LOGIC := '0';
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN
UUT: SYN_UP_DOWN PORT MAP (
MODE => MODE,
CLK => CLK,
Q => Q
);
CLK_PROCESS :PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_PERIOD/2;
CLK <= '1';
END PROCESS;
STIM_PROC: PROCESS
BEGIN
MODE<='1','0' AFTER 80 NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------
OUTPUT

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COMPONENTS USED
1.T FLIPFLOP
LIBRARY IEEE;
ENTITY TFF IS
PORT ( T,CLK : IN STD_LOGIC;
END TFF;
ARCHITECTURE BEHAVIORAL OF TFF IS
SIGNAL S: STD_LOGIC:='0';
BEGIN
Q<=S;
QBAR<= NOT S;
PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
IF(T='1') THEN
S<=NOT S;
ELSE S<=S;
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;
2. AND GATE
LIBRARY IEEE;
ENTITY AND_GATE IS
Y : OUT STD_LOGIC);
END NOTGATE;
BEGIN
PROCESS(A,B)
BEGIN
IF (A='1' AND B=’1’) THEN Y<='1' ;

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ELSE Y<='0';
END IF;
END PROCESS;
END BEHAVIORAL;
3.OR GATE
LIBRARY IEEE;
ENTITY OR_GATE IS
Y : OUT STD_LOGIC);
END NOTGATE;
BEGIN
PROCESS(A,B)
BEGIN
IF (A='0' AND B=’0’) THEN Y<='0' ;
ELSE Y<='1';
END IF;
END PROCESS;
END BEHAVIORAL;
5.NOT GATE
LIBRARY IEEE;
ENTITY NOTGATE IS
Y : OUT STD_LOGIC);
END NOTGATE;
ARCHITECTURE BEHAVIORAL OF NOTGATE IS
BEGIN
PROCESS(A)
BEGIN

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66
IF A='1' THEN Y<='0' ;
ELSE Y<='1';
END IF;
END PROCESS;
END BEHAVIORAL;
RESULT
Implemented synchronous UP/DOWN counter in structural model and variefied the output.
SYNTHESIS REPORT
========================================================================
* Final Report *
========================================================================
Final Results
RTL Top Level Output File Name : Syn_up_down.ngr
Top Level Output File Name : Syn_up_down
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 6
Cell Usage :
# BELS : 8
# INV : 4
# LUT2 : 1
# LUT3 : 1
# LUT4 : 1
# VCC : 1
# FDE : 4
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 5
# IBUF : 1
# OBUF : 4

HDL Lab Report
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Number of IOs: 6

HDL Lab Report
68
9.RING COUNTER
AIM
To simulate a half adder in data flow model
THEORY
In this program a 4 bit ring counter is implemented.A 4 bit ring counter consist of 4D flip
flops .The output of the rightmost DFF is fed into the input of first DFF.Initially a ‘1’ is set as output
of first DFF using prest pin.Then this bit will shift for each clock cycle.Ring counter has 4 states-
0001,0010,0100,1000.
CIRCUIT DIAGRAM
SCHEMATIC DIAGRAM

HDL Lab Report
69
VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY RING_COUNTER IS
PORT ( CLK ,PR: IN STD_LOGIC;
END RING_COUNTER;
ARCHITECTURE BEHAVIORAL OF RING_COUNTER IS
COMPONENT D_FF
PORT ( D,CLK,PR,CLR : IN STD_LOGIC;
Q ,QBAR: OUT STD_LOGIC );
END COMPONENT;
SIGNAL S : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
A0: D_FF PORT MAP(S(3),CLK,PR,'0',S(0));
A1: D_FF PORT MAP(S(0),CLK,'0','0',S(1));
Q<=S;
END BEHAVIORAL;
-------------------------------------------------------------------

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TEST BENCH:
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_RING IS
END TB_RING;
ARCHITECTURE BEHAVIOR OF TB_RING IS
COMPONENT RING_COUNTER
PORT(
CLK : IN STD_LOGIC;
PR : IN STD_LOGIC;
);
END COMPONENT;
BEGIN
UUT: RING_COUNTER PORT MAP (
CLK => CLK,
PR => PR,
Q => Q );

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BEGIN
CLK <= '0';
CLK <= '1';
END PROCESS;
STIM_PROC: PROCESS
BEGIN
PR<='1','0' AFTER 2 NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------
COMPONENTS USED
-------------------------------------------------------------------
D FLIP FLOP
LIBRARY IEEE;
ENTITY D_FF IS
Q ,QBAR: OUT STD_LOGIC );
END D_FF;

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SIGNAL S: STD_LOGIC :='0';
BEGIN
Q<=S;
PROCESS(CLK,CLR,PR)
BEGIN
IF(CLR='1' AND PR='0') THEN
S<='0';
S<='1';
ELSIF (PR='1' AND CLR='1') THEN
S<='X';
IF (RISING_EDGE(CLK)) THEN
IF(D='0') THEN
S<='0';
ELSIF(D='1') THEN S<='1';
END IF;
END IF;
END IF;
QBAR<=NOT S;
END PROCESS;
END BEHAVIORAL;
-------------------------------------------------------------------

HDL Lab Report
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OUTPUT
RESULT
Implemented ring counter and verified the result.
SYNTHESIS REPORT
========================================================================
* Final Report *
========================================================================
Final Results
RTL Top Level Output File Name : ring_counter.ngr
Top Level Output File Name : ring_counter
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 6
Cell Usage :
# BELS : 3
# GND : 1

HDL Lab Report
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# INV : 1
# VCC : 1
# FDCPE : 4
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 5
# IBUF : 1
# OBUF : 4
========================================================================
Number of IOs: 6

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10.JHONSON COUNTER
AIM
To implement a 4-bit jhonson counter using D flip flop.
THEORY
In this program a 4 bit Johnson counter is implemented using four D flip flops. The output
Qbar of last DFF is given as input to the first DFF. Johnson counter has 8 states0000,1000,
1100,1110,1111,0111,0011,0001.
CIRCUIT DIAGRAM
SCEMATIC DIAGRAM

HDL Lab Report
76
VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY JHONSON_COUNTER IS
PORT ( CLK ,PR: IN STD_LOGIC;
END JHONSON_COUNTER;
ARCHITECTURE BEHAVIORAL OF JHONSON_COUNTER IS
COMPONENT D_FF
Q ,QBAR: OUT STD_LOGIC
);
END COMPONENT;
SIGNAL S,P : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
A0: D_FF PORT MAP(P(3),CLK,'0','0',S(0),P(0));
A1: D_FF PORT MAP(S(0),CLK,'0','0',S(1),P(1));
Q<=S;
END BEHAVIORAL;
-------------------------------------------------------------------

HDL Lab Report
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TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_JHONSON_COUNTER IS
END TB_JHONSON_COUNTER;
ARCHITECTURE BEHAVIOR OF TB_JHONSON_COUNTER IS
COMPONENT JHONSON_COUNTER
PORT(
CLK : IN STD_LOGIC;
PR : IN STD_LOGIC;
);
END COMPONENT;
BEGIN
UUT: JHONSON_COUNTER PORT MAP (
CLK => CLK,
PR => PR,
Q => Q );
BEGIN

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CLK <= '0';
CLK <= '1';
END PROCESS;
STIM_PROC: PROCESS
BEGIN
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------
OUTPUT
RESULT
Implemented jhonson counter and verified the output.
SYNTHESIS REPORT
========================================================================
* Final Report *
========================================================================
Final Results
RTL Top Level Output File Name : jhonson_counter.ngr
Top Level Output File Name : jhonson_counter
Output Format : NGC
Keep Hierarchy : No

HDL Lab Report
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Design Statistics
# IOs : 6
Cell Usage :
# BELS : 3
# GND : 1
# INV : 1
# VCC : 1
# FDCPE : 4
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 4
# OBUF : 4
========================================================================
Number of IOs: 6

HDL Lab Report
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11.SHIFT REGESTER
AIM:
To design a shift register which works in the following modes.
Mode= 00 => SISO
Mode= 01 => PISO
Mode= 10 => SIPO
Mode= 11 => PIPO
THEORY:
Shift register that shifts by one position the bit array stored in it, shifting in the data present at
its input and shifting out the last bit in the array, at each transition of the clock input.Shift registers
can have both parallel and serial inputs and outputs. These are often configured as serial-in, parallel-
out (SIPO) or as parallel-in, serial-out (PISO). There are also types that have both serial and parallel
input and types with serial and parallel output.
SCHEMATIC DIAGRAM:
VHDL CODE:
-------------------------------------------------------------------
LIBRARY IEEE;

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ENTITY SHIFT_REG IS
MODE : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
LOAD,SERIAL_IN,SHIFT,CLOCK : IN STD_LOGIC;
SERIAL_OUT : OUT STD_LOGIC;
P : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END SHIFT_REG;
ARCHITECTURE BEHAVIORAL OF SHIFT_REG IS
SIGNAL M:STD_LOGIC:='0';
SIGNAL N:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
PROCESS(CLOCK)
BEGIN
IF(LOAD='1' AND SHIFT='0') THEN M<=SERIAL_IN;
N<=I;
ELSIF(LOAD='0' AND SHIFT='1') THEN
IF(CLOCK='1' AND CLOCK'EVENT) THEN
CASE MODE IS
WHEN "00"=> SERIAL_OUT<=SERIAL_IN;
WHEN "01"=> N<=SERIAL_IN & N(3 DOWNTO 1);
WHEN "10"=> SERIAL_OUT<=N(0);
N<=N(0) & N(3 DOWNTO 1);
WHEN "11"=> P<=I;
WHEN OTHERS =>NULL;
END CASE;
END IF;

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END IF;
END PROCESS;
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH:
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_SHIFT IS
END TB_SHIFT;
ARCHITECTURE BEHAVIOR OF TB_SHIFT IS
COMPONENT SHIFT_REG
PORT(
MODE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
LOAD : IN STD_LOGIC;
SERIAL_IN : IN STD_LOGIC;
SHIFT : IN STD_LOGIC;
SERIAL_OUT : OUT STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);

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END COMPONENT;
--INPUTS
SIGNAL MODE : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL LOAD : STD_LOGIC := '0';
SIGNAL SERIAL_IN : STD_LOGIC := '0';
SIGNAL SHIFT : STD_LOGIC := '0';
--OUTPUTS
SIGNAL SERIAL_OUT : STD_LOGIC;
SIGNAL P : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
UUT: SHIFT_REG PORT MAP (
I => I,
MODE => MODE,
LOAD => LOAD,
SERIAL_IN => SERIAL_IN,
SHIFT => SHIFT,
CLOCK => CLOCK,

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84
SERIAL_OUT => SERIAL_OUT,
P => P
);
BEGIN
CLOCK <= '0';
CLOCK <= '1';
END PROCESS;
-- STIMULUS PROCESS
STIM_PROC: PROCESS
BEGIN
I<="1001","1111" AFTER 150 NS;
SERIAL_IN<='1','0' AFTER 20 NS,'1' AFTER 35 NS,'1' AFTER 50 NS,'0'
AFTER 60 NS;
LOAD<='1','0' AFTER 5 NS,'1' AFTER 40 NS,'0' AFTER 45 NS,'1' AFTER
80 NS,'0' AFTER 82 NS,'1' AFTER 100 NS,'0' AFTER 102 NS,'1' AFTER
200 NS,'0' AFTER 205 NS,'1' AFTER 280 NS,'0' AFTER 285 NS;
SHIFT<='0','1' AFTER 10 NS,'0' AFTER 40 NS,'1' AFTER 45 NS,'0'
AFTER 80 NS,'1' AFTER 82 NS,'0' AFTER 100 NS,'1' AFTER 102 NS,'0'
AFTER 200 NS,'1' AFTER 205 NS,'0' AFTER 280 NS,'1' AFTER 285 NS;
MODE<="00","01" AFTER 40 NS,"11" AFTER 80 NS,"10" AFTER 100 NS,"11"
AFTER 200 NS,"10" AFTER 280 NS;
WAIT;
END PROCESS;
END;

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OUTPUT:
SYNTHESIS REPORT:
========================================================================
* Final Report *
========================================================================
Final Results
RTL Top Level Output File Name : shift_reg.ngr
Top Level Output File Name : shift_reg
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 15
Cell Usage :
# BELS : 18
# LUT2 : 1
# LUT3 : 9
# LUT3_L : 1
# LUT4 : 6

HDL Lab Report
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# MUXF5 : 1
# FDCPE : 4
# FDE : 5
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 14
# IBUF : 9
# OBUF : 5
========================================================================
Number of IOs: 15
IOB Flip Flops: 4

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87
12.a SEQUENCE DETECTOR FOR 010 USING MOORE MECHINE
AIM
To design a MOORE state machine to detect the sequence 010 without reset.
STATE DIAGRAM
SCHEMATIC DIAGRAM

HDL Lab Report
88
VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY MOORE010 IS
PORT ( CLK,DIN,RESET : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END MOORE010;
ARCHITECTURE BEHAVIORAL OF MOORE010 IS
TYPE STATE_TYPE IS (S0,S1,S2,S3);
SIGNAL STATE :STATE_TYPE := S0;
SIGNAL SCLK :STD_LOGIC:='0';
BEGIN
PROCESS(CLK,RESET)
BEGIN
IF(RESET='0') THEN
IF(CLK = '1' AND CLK'EVENT) THEN
CASE STATE IS
WHEN S0 => Y<='0';
IF(DIN ='0') THEN STATE <= S1;
ELSE STATE <= S0; END IF;
WHEN S1 => Y<='0';

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89
WHEN S2 => Y<='0';
WHEN S3 => Y<='1';
END CASE;
ELSE NULL;
END IF;
END IF;
END PROCESS ;
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_MOORE_010_NEW IS
END TB_MOORE_010_NEW;
ARCHITECTURE BEHAVIOR OF TB_MOORE_010_NEW IS

HDL Lab Report
90
COMPONENT MOORE010
PORT(
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC;
RESET : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL DIN : STD_LOGIC := '0';
SIGNAL RESET : STD_LOGIC := '0';
SIGNAL Y : STD_LOGIC;
BEGIN
UUT: MOORE010 PORT MAP (
CLK => CLK,
DIN => DIN,
RESET => RESET,
Y => Y
);
BEGIN

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CLK <= '0';
CLK <= '1';
END PROCESS;
STIM_PROC: PROCESS
BEGIN
DIN <= '0','1' AFTER 50 NS,'1' AFTER 100 NS,'0' AFTER 150
NS,'1' AFTER 200 NS,'0' AFTER 250 NS,'1' AFTER 300 NS,'0' AFTER
350 NS,'1' AFTER 400 NS,'0' AFTER 450 NS,'1' AFTER 500 NS,'0'
AFTER 550 NS,'0' AFTER 600 NS,'1' AFTER 650 NS,'0' AFTER 700
AFTER 1100 NS,'0' AFTER 1150 NS;
WAIT;
END PROCESS;
END;
OUTPUT
RESULT
Implemented MOORE machine to detect the sequence 010 and verified the
output.
SYNTHESIS REPORT

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=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : moore010.ngr
Top Level Output File Name : moore010
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 4
Cell Usage :
# BELS : 4
# INV : 2
# LUT2 : 1
# LUT3 : 1
# FDE : 3
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 3
# IBUF : 2
# OBUF : 1
=========================================================================
Number of IOs: 4

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12.b SEQUENCE DETECTOR FOR 010 USING MEALY MECHINE
AIM
To design a mealy state machine to detect 010 without reset.
STATE DIAGRAM
SCHEMATIC DIAGRAM

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VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY MEALY010 IS
PORT ( CLK,DIN : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END MEALY010;
ARCHITECTURE BEHAVIORAL OF MEALY010 IS
TYPE STATE_TYPE IS (S0,S1,S2);
SIGNAL STATE :STATE_TYPE := S0;
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK = '0' AND CLK'EVENT) THEN
CASE STATE IS
WHEN S0 => IF(DIN ='0') THEN STATE <= S1; Y<='0';
ELSE STATE <= S0; Y <= '0'; END IF;

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END CASE;
END IF;
END PROCESS;
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_MEALY010 IS
END TB_MEALY010;
ARCHITECTURE BEHAVIOR OF TB_MEALY010 IS
COMPONENT MEALY010
PORT(
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;

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BEGIN
UUT: MEALY010 PORT MAP (
CLK => CLK,
DIN => DIN,
Y => Y );
BEGIN
CLK <= '0';
CLK <= '1';
END PROCESS;
STIM_PROC: PROCESS
BEGIN
DIN <= '0','1' AFTER 50 NS,'1' AFTER 100 NS,'0' AFTER 150
AFTER 550 NS,'0' AFTER 600 NS,'1' AFTER 650 NS,'0' AFTER 700
AFTER 1100 NS,'0' AFTER 1150 NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------

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OUTPUT
RESULT
Implemented mealy machine to detect the sequence 010.
SYNTHESIS REPORT
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : mealy010.ngr
Top Level Output File Name : mealy010
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 3
Cell Usage :
# BELS : 3
# GND : 1
# INV : 2
# FDR_1 : 2
# FDS_1 : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 2
# IBUF : 1
# OBUF : 1
=========================================================================

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Number of IOs: 3

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99
12.c SEQUENCE DETECTOR FOR 110 OR 0011
AIM:
Design a sequence detector to detect the sequences 110 or 0011 without reset.
STATE DIAGRAM:

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SCHEMATIC DIAGRAM:
VHDL CODE:
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY MEALY IS
PORT ( X,CLOCK,RESET : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END MEALY;
ARCHITECTURE BEHAVIORAL OF MEALY IS
TYPE STATE_TYPE IS (S0,S1,S2,S3,S4,S5,S6,S7);
SIGNAL STATE:STATE_TYPE:=S0;
SIGNAL COUNT:INTEGER RANGE 0 TO 100000000;
--SIGNAL CLOCK:STD_LOGIC;

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BEGIN
PROCESS(CLOCK,RESET)
BEGIN
IF(RESET='1') THEN STATE<=S0;
ELSIF (CLOCK='1' AND CLOCK'EVENT) THEN
CASE STATE IS
WHEN S0=> IF(X='1') THEN STATE<=S1; Y<='0';
ELSIF(X='0') THEN STATE<=S2; Y<='0';
END IF;
END IF;
END IF;
END IF;
END IF;

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END IF;
END IF;
END IF;
END CASE;
END IF;
END PROCESS;
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH:
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_MEALY IS
END TB_MEALY;
ARCHITECTURE BEHAVIOR OF TB_MEALY IS

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COMPONENT MEALY
PORT(
X : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;
--INPUTS
SIGNAL X : STD_LOGIC := '0';
--OUTPUTS
BEGIN
UUT: MEALY PORT MAP (
X => X,
CLOCK => CLOCK,

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RESET => RESET,
Y => Y
);
BEGIN
CLOCK <= '1';
CLOCK <= '0';
END PROCESS;
-- STIMULUS PROCESS
STIM_PROC: PROCESS
BEGIN
RESET<='1','0' AFTER 2 NS;
X<='0','1' AFTER 10 NS,'0' AFTER 30 NS,'1' AFTER 50 NS,'0' AFTER 70
NS,'1' AFTER 80 NS,'0' AFTER 110 NS,'1' AFTER 140 NS,'0' AFTER 150
NS,'1' AFTER 160 NS,'0' AFTER 170 NS,'1' AFTER 190 NS,'0' AFTER 210
NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------

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OUTPUT:
SYNTHESIS REPORT:
========================================================================
* Final Report *
========================================================================
Final Results
RTL Top Level Output File Name : mealy.ngr
Top Level Output File Name : mealy
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 4
Cell Usage :
# BELS : 11
# GND : 1
# INV : 1
# LUT2 : 3

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# LUT2_L : 1
# LUT4 : 5
# FDC : 7
# FDE : 1
# FDP : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 3
# IBUF : 2
# OBUF : 1
========================================================================
Number of IOs: 4

HDL Lab Report
107
13. XS-3 BCD CONVERTER
AIM
To implement a sequential circuit which converts XS-3 to BCD .
THEORY
Input to the circuit will be provided on each clock cycle (LSB to MSB) and the
corresponding output(LSB to MSB) will be shown on that clock pulse itself.
TRUTH TABLE
XS_3 CODE INPUT BCD OUTPUT
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

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STATE DIAGRAM
SCHEMATIC DIAGRAM

HDL Lab Report
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VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY XS3TOBCD IS
PORT ( CLK,DIN,RESET : IN STD_LOGIC;
DOUT : OUT STD_LOGIC);
END XS3TOBCD;
ARCHITECTURE BEHAVIORAL OF XS3TOBCD IS
TYPE STATE_TYPE IS(S0,S1,S2,S3,S4,S5,S6);
BEGIN
PROCESS(CLK,RESET)
BEGIN
IF(RESET='0') THEN
IF(CLK='1' AND CLK'EVENT) THEN
CASE STATE IS
WHEN S0 => IF(DIN='1') THEN STATE<=S1;DOUT<='0';
ELSE STATE<=S2;DOUT<='1'; END IF;

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END CASE;
END IF;
ELSE STATE<=S0;DOUT<='0';
END IF;
END PROCESS;
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_XS3TOBCD IS
END TB_XS3TOBCD;
ARCHITECTURE BEHAVIOR OF TB_XS3TOBCD IS
COMPONENT XS3TOBCD
PORT(
CLK : IN STD_LOGIC;

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111
DIN : IN STD_LOGIC;
DOUT : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL DOUT : STD_LOGIC;
BEGIN
UUT: XS3TOBCD PORT MAP (
CLK => CLK,
DIN => DIN,
RESET => RESET,
DOUT => DOUT
);
BEGIN
CLK <= '0';
CLK <= '1';
END PROCESS;

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STIM_PROC: PROCESS
BEGIN
RESET<='0','1' AFTER 40NS,'0' AFTER 50 NS;
DIN<='0','1' AFTER 12 NS,'1' AFTER 22 NS,'0' AFTER 32 NS,'1'
AFTER 52 NS,'1' AFTER 62 NS,'1' AFTER 72 NS,'0' AFTER 82 NS;
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------
OUTPUT
RESULT
Implemented XS-3 to BCD converter and verified the output.
SYNTHESIS REPORT
========================================================================
Final Report
========================================================================
Final Results
RTL Top Level Output File Name : xs3tobcd.ngr
Top Level Output File Name : xs3tobcd
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 4

HDL Lab Report
113
Cell Usage :
# BELS : 10
# LUT2 : 3
# LUT3 : 6
# MUXF5 : 1
# FDC : 7
# FDP : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 3
# IBUF : 2
# OBUF : 1
========================================================================
Number of IOs: 4

HDL Lab Report
114
14.TRAFFIC LIGHT CONTROLLER
AIM:
1. The traffic light has 2 signals-GREEN which indicates the vehicles to pass and RED which
indicates the vehicles to stop.The period for which each incoming branch of the 4 way
junction has its GREEN signal as ON in 5 seconds after which it turns to RED and the
GREEN for next direction is ON.
2. Each direction has an emergency switch associated with it.If the emergency switch
associated with a particular incoming branch is activated, it overrides the current
configuration of the traffic light and allows the movement of vehicles from that particular
branch for next 10 seconds.After 10 seconds the old configuration is restored.
1.TRAFFIC LIGHT WITHOUT EMERGENCY SWITCH
STATE DIAGRAM:
In S0 the green light of traffic light post A is ON.
S1 the green light of traffic light post B is ON.

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SCHEMATIC
VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TRAFFIC_2 IS
PORT ( CLOCK: IN STD_LOGIC;
G_A,R_A,G_B,R_B,G_C,R_C,G_D,R_D : OUT STD_LOGIC);
END TRAFFIC_2;
ARCHITECTURE BEHAVIORAL OF TRAFFIC_2 IS
TYPE STATE_TYPE IS (S0,S1,S2,S3);
SIGNAL STATE:STATE_TYPE;
SIGNAL COUNT:INTEGER RANGE 0 TO 10;

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BEGIN
PROCESS(CLOCK)
BEGIN
IF (CLOCK='1' AND CLOCK'EVENT) THEN
CASE STATE IS
WHEN S0=> G_A<='1';
R_A<='0';
G_B<='0';
R_B<='1';
G_C<='0';
R_C<='1';
G_D<='0';
R_D<='1';
IF COUNT<4 THEN STATE<=S0; COUNT<=COUNT+1;
ELSE STATE<=S1; COUNT<=0;
END IF;
WHEN S1=> G_A<='0';
R_A<='1';
G_B<='1';
R_B<='0';

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G_C<='0';
R_C<='1';
G_D<='0';
R_D<='1';
END IF;
WHEN S2=> G_A<='0';
R_A<='1';
G_B<='0';
R_B<='1';
G_C<='1';
R_C<='0';
G_D<='0';
R_D<='1';
END IF;

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WHEN S3=> G_A<='0';
R_A<='1';
G_B<='0';
R_B<='1';
G_C<='0';
R_C<='1';
G_D<='1';
R_D<='0';
END IF;
END CASE;
END IF;
END PROCESS P2;
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_TRAFFIC_2 IS
END TB_TRAFFIC_2;

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ARCHITECTURE BEHAVIOR OF TB_TRAFFIC_2 IS
COMPONENT TRAFFIC_2
PORT(
G_A : OUT STD_LOGIC;
R_A : OUT STD_LOGIC;
G_B : OUT STD_LOGIC;
R_B : OUT STD_LOGIC;
G_C : OUT STD_LOGIC;
R_C : OUT STD_LOGIC;
G_D : OUT STD_LOGIC;
R_D : OUT STD_LOGIC
);
END COMPONENT;
--INPUTS
--OUTPUTS
SIGNAL G_A : STD_LOGIC;
SIGNAL R_A : STD_LOGIC;
SIGNAL G_B : STD_LOGIC;

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SIGNAL R_B : STD_LOGIC;
SIGNAL G_C : STD_LOGIC;
SIGNAL R_C : STD_LOGIC;
SIGNAL G_D : STD_LOGIC;
SIGNAL R_D : STD_LOGIC;
CONSTANT SCLOCK_PERIOD : TIME := 1 NS;
BEGIN
UUT: TRAFFIC_2 PORT MAP (
CLOCK => CLOCK,
G_A => G_A,
R_A => R_A,
G_B => G_B,
R_B => R_B,
G_C => G_C,
R_C => R_C,
G_D => G_D,
R_D => R_D
);

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BEGIN
CLOCK <= '0';
WAIT FOR SCLOCK_PERIOD/2;
CLOCK <= '1';
WAIT FOR SCLOCK_PERIOD/2;
END PROCESS;
-- STIMULUS PROCESS
STIM_PROC: PROCESS
BEGIN
WAIT;
END PROCESS;
END;
OUTPUT
SYNTHESIS REPORT
========================================================================
Final Report
========================================================================
Final Results
RTL Top Level Output File Name : traffic_2.ngr
Top Level Output File Name : traffic_2

HDL Lab Report
122
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 10
Cell Usage :
# BELS : 137
# GND : 1
# INV : 3
# LUT1 : 24
# LUT2 : 25
# LUT2_D : 2
# LUT3 : 3
# LUT4 : 19
# LUT4_L : 1
# MUXCY : 31
# MUXF5 : 2
# VCC : 1
# XORCY : 25
# FDC : 39
# FDCE : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 9

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# IBUF : 1
# OBUF : 8
========================================================================
Number of IOs: 10

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2.TRAFFIC LIGHT EMERGENCY SWITCH
SCHEMATIC DIAGRAM:
VHDL CODE
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TRAFFIC_2 IS
PORT ( CLOCK,S_A,S_B,S_C,S_D : IN STD_LOGIC;
G_A,R_A,G_B,R_B,G_C,R_C,G_D,R_D : OUT STD_LOGIC);
END TRAFFIC_2;
ARCHITECTURE BEHAVIORAL OF TRAFFIC_2 IS
TYPE STATE_TYPE IS (S0,S1,S2,S3,S4,S5,S6,S7);
SIGNAL COUNT:INTEGER RANGE 0 TO 10:=0;
SIGNAL COUNT_1:INTEGER RANGE 0 TO 15:=0;

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SIGNAL K,M:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
M<=S_A&S_B&S_C&S_D;
PROCESS(CLOCK)
BEGIN
IF (CLOCK='1' AND CLOCK'EVENT) THEN
CASE STATE IS
WHEN S0=>
IF(M="1000") THEN STATE<=S4;K<="1000";
ELSIF(M="0100") THEN STATE<=S5;K<="1000";
ELSE G_A<='1';
R_A<='0';
G_B<='0';
R_B<='1';
G_C<='0';
R_C<='1';
G_D<='0';
R_D<='1';
END IF;
END IF;

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WHEN S1=>
IF(M="1000") THEN STATE<=S4;K<="0100";
ELSE G_A<='0';
R_A<='1';
G_B<='1';
R_B<='0';
G_C<='0';
R_C<='1';
G_D<='0';
R_D<='1';
END IF;
END IF;
WHEN S2=>
IF(M="1000") THEN STATE<=S4;K<="0010";

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ELSE G_A<='0';
R_A<='1';
G_B<='0';
R_B<='1';
G_C<='1';
R_C<='0';
G_D<='0';
R_D<='1';
END IF;
END IF;
WHEN S3=>
IF(M="1000") THEN STATE<=S4;K<="0001";
ELSE G_A<='0';
R_A<='1';
G_B<='0';
R_B<='1';

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G_C<='0';
R_C<='1';
G_D<='1';
R_D<='0';
END IF;
END IF;
WHEN S4=> IF (COUNT_1< 9) THEN
G_A<='1';
R_A<='0';
G_B<='0';
R_B<='1';
G_C<='0';
R_C<='1';
G_D<='0';
R_D<='1';
COUNT_1<= COUNT_1+1;
STATE<= S4;
ELSE COUNT_1<=0;
CASE K IS

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WHEN "1000"=> STATE<= S0;
WHEN OTHERS=> NULL;
END CASE;
K<="0000";
END IF;
G_A<='0';
R_A<='1';
G_B<='1';
R_B<='0';
G_C<='0';
R_C<='1';
G_D<='0';
R_D<='1';
STATE<= S5;
ELSE COUNT_1<=0;
CASE K IS

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WHEN OTHERS=> NULL;
END CASE;
K<="0000";
END IF;
G_A<='0';
R_A<='1';
G_B<='0';
R_B<='1';
G_C<='1';
R_C<='0';
G_D<='0';
R_D<='1';
STATE<= S6;
ELSE COUNT_1<=0;
CASE K IS

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WHEN OTHERS=> NULL;
END CASE;
K<="0000";
END IF;
G_A<='0';
R_A<='1';
G_B<='0';
R_B<='1';
G_C<='0';
R_C<='1';
G_D<='1';
R_D<='0';
STATE<= S7;
ELSE COUNT_1<=0;
CASE K IS

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WHEN OTHERS=> NULL;
END CASE;
K<="0000";
END IF;
END CASE;
END IF;
END PROCESS;
END BEHAVIORAL;
-------------------------------------------------------------------
TEST BENCH
-------------------------------------------------------------------
LIBRARY IEEE;
ENTITY TB_TRAFFIC_CONTROLLR IS
END TB_TRAFFIC_CONTROLLR;
ARCHITECTURE BEHAVIOR OF TB_TRAFFIC_CONTROLLR IS
COMPONENT TRAFFIC_2
PORT(

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S_A : IN STD_LOGIC;
S_B : IN STD_LOGIC;
S_C : IN STD_LOGIC;
S_D : IN STD_LOGIC;
G_A : OUT STD_LOGIC;
R_A : OUT STD_LOGIC;
G_B : OUT STD_LOGIC;
R_B : OUT STD_LOGIC;
G_C : OUT STD_LOGIC;
R_C : OUT STD_LOGIC;
G_D : OUT STD_LOGIC;
R_D : OUT STD_LOGIC
);
END COMPONENT;
--INPUTS
SIGNAL S_A : STD_LOGIC := '0';
SIGNAL S_B : STD_LOGIC := '0';
SIGNAL S_C : STD_LOGIC := '0';
SIGNAL S_D : STD_LOGIC := '0';
--OUTPUTS
SIGNAL G_A : STD_LOGIC;
SIGNAL R_A : STD_LOGIC;
SIGNAL G_B : STD_LOGIC;

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SIGNAL R_B : STD_LOGIC;
SIGNAL G_C : STD_LOGIC;
SIGNAL R_C : STD_LOGIC;
SIGNAL G_D : STD_LOGIC;
SIGNAL R_D : STD_LOGIC;
BEGIN
UUT: TRAFFIC_2 PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
S_A => S_A,
S_B => S_B,
S_C => S_C,
S_D => S_D,
G_A => G_A,
R_A => R_A,
G_B => G_B,
R_B => R_B,
G_C => G_C,
R_C => R_C,
G_D => G_D,
R_D => R_D
);

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BEGIN
CLOCK <= '0';
CLOCK <= '1';
END PROCESS;
-- STIMULUS PROCESS
STIM_PROC: PROCESS
BEGIN
S_A<='0';
S_B<='0';
S_C<='0';
S_D<='0';
WAIT FOR 15 NS;
S_A<='0';
S_B<='1';
S_C<='0';
S_D<='0';
WAIT FOR 5 NS;
S_A<='0';
S_B<='0';

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S_C<='0';
S_D<='0';
WAIT;
END PROCESS;
END;
-------------------------------------------------------------------
OUTPUT
SYNTHESIS REPORT
========================================================================
* Final Report *
========================================================================
Final Results
RTL Top Level Output File Name : traffic_2.ngr
Top Level Output File Name : traffic_2
Output Format : NGC
Keep Hierarchy : No
Design Statistics

HDL Lab Report
137
# IOs : 14
Cell Usage :
# BELS : 45
# LUT2_L : 1
# LUT3 : 4
# LUT3_L : 1
# LUT4 : 30
# LUT4_D : 2
# LUT4_L : 6
# MUXF5 : 1
# FD : 22
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 12
# IBUF : 4
# OBUF : 8
========================================================================
Number of IOs: 14

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