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High Speed Electrical Testing  Jim Choate Intel Corporation
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object]
Goals of the Electrical Compliance Program ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
New Testing Areas ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],HS Electrical Test Spec On USB-IF Members Site
USB HS Electrical Test Modes ,[object Object]
General HS Electrical Test Procedure ,[object Object],[object Object],[object Object],[object Object]
New Test Fixture(s) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],USB HS Test Fixture HS Relay Test Port Initialization Port Diff Probe Data Generator 90 Ohms Power Selection Ckt Vbus1 Vbus2 Vcc Gnd
New Test Fixture(s) High Speed Device Signal Quality Test Fixture Test Port Init Port To Host  Controller To Device  Under Test Isolation relay power Test Switch Diff Probe Test Point
HS Signal Quality Test Procedure ,[object Object],[object Object],[object Object],[object Object],[object Object],90  Oscilloscope USB HS Test Fixture HS Relay Test Mode   SW Differential Probe Device Under Test
Eye Pattern Generation ,[object Object]
Eye Pattern Generation ,[object Object],[object Object],[object Object],[object Object]
Eye Pattern Generation ,[object Object],Reference points between runs ignored Optimized reference point Actual crossover
Eye Pattern Generation ,[object Object],[object Object],1 bit time
Passing Eye Pattern ,[object Object]
Failing Eye Patterns ,[object Object],[object Object],[object Object],[object Object]
HS Device Receiver Sensitivity and Squelch Test Procedure ,[object Object],[object Object],[object Object],[object Object],[object Object],Data Generator Test Mode   SW USB 2.0 Test Fixture HS Relay SMA Device under test
HS Device Receiver Sensitivity and Squelch Test Results ,[object Object],[object Object],[object Object],DG packet Device Response No Device Response Minimum Receiver sensitivity threshold
TDR Test Procedure ,[object Object],[object Object],[object Object],[object Object],TDR Test Mode   SW USB 2.0 Test Fixture HS Relay SMA Device Under Test
TDR Test Procedure ,[object Object],[object Object],[object Object],[object Object],Open voltage step indicates  connector  reference location
TDR Test Procedure ,[object Object],ZHSTHRU 70 to 110 Ohms (red cursors) ZHSTERM 80 to 100 Ohms (yellow region) USB connector Excursion of ZHSTHRU passes  using exception window
TDR Test Procedure ,[object Object],[object Object],Violates ZHSTHRU for > 800ps
Other Test Modes ,[object Object],[object Object],[object Object],[object Object],[object Object]
Conclusions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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Choate hs elec_test_final

  • 1.  
  • 2. High Speed Electrical Testing Jim Choate Intel Corporation
  • 3.
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  • 7.
  • 8.
  • 9. New Test Fixture(s) High Speed Device Signal Quality Test Fixture Test Port Init Port To Host Controller To Device Under Test Isolation relay power Test Switch Diff Probe Test Point
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Notes de l'éditeur

  1. Test modes enable repeatable testing The first assertion in the test spec is test mode support high speed electrical testing is much more comprehensive because of test modes
  2. Testing at TP2