SlideShare une entreprise Scribd logo
1  sur  5
Télécharger pour lire hors ligne
International Journal of Computer Applications Technology and Research
Volume 3– Issue 6, 390 - 394, 2014
www.ijcat.com 390
Design and Implementation of Refresh and Timing
Controller Unit for LPDDR2 Memory Controller
Sandya M.J
Dept. of Electronics and
communication
BNM Institute Of Technology
Bangalore,India
Chaitra .N
Dept. of Electronics and
communication
BNM Institute Of Technology
Bangalore,India
Ramudu B
Graphene Semiconductor India
Pvt Ltd
Bangalore,India
Abstract: this paper presents a “Implementation of “Refresh And Timing Controller” unit for low power double data rate 2 memory
controller (LPDDR2 MEMORY CONTROLLER). “Refresh and Timing Controller” unit plays a vital role for LPDDR2 memory
controller .It maintains different timing parameters to handle various commands for memory like refresh, read and write operations and
also performs Memory Initialization. Since it is low power DDR2 the maximum duration in power-down mode and deep power down
mode is maintained by “Refresh and Timing Controller” unit. The refresh rate period is programmable using the Refresh Period
Register. It supports “All Bank Refresh”. The unit has timers to accommodate Refresh, Read/Write, and Power down modes. The RTL
is done using the System Verilog. The design is simulated
Keywords: LPDDR2 MC; Design; Device initialization; Refresh requirement;Timing parameters
1. INTRODUCTION
Embedded systems usually have a limited amount of memory
available; this is because of cost, size, power, weight or other
constraints imposed by the overall system requirements. It
may be necessary to control how this memory is allocated so
that it can be used effectively. Handheld device like mobile,
tablet etc are battery operated. For long time battery lasting
better power optimization is required in those devices.
Nowadays the devices are having multiple masters and share
common memory for their applications. LPDDR2 is better fit
for these kinds of devices. LPDDR2 memories consume low
power. LPDDR2 memory controller accepts write/read
commands from multiple masters and generates memory
related commands. Functions of memory controller are
 solves different bandwidth requirement issues
 handles the “refresh” cycle for Memory.
 handles read and write operations with
bank/row/column addressing.
Since these memories are made with capacitors, charge will
leak continuously so refreshing is required memory controller
will generate refresh commands as specified in JEDEC
specification. For each refresh in a LPDDR2 row, the stored
information in each cell is read out and then written back to
itself as each LPDDR2 bit read is self-destructive. The refresh
process is inevitable for maintaining data correctness,
unfortunately, at the expense of power and bandwidth
overhead.
This paper is organized as follows. The brief introduction to
“Refresh And Timing Controller” “is given in section 2
describes top module of“ Refresh And Timing Controller”,
section 3 describes the implementation of “Refresh And
Timing Controller” for LPDDR2 memory controller. Section
4 describes the result and analysis.
Figure 1: LPDDR2 Memory controller
See figure 1 the LPDDR2 memory controller,LPDDR2
MC‟s are used to drive DDR2 SDRAM, where data is
transferred on the rising and falling access of the memory
clock of the system without increasing the clock rate or
increasing the bus width to the memory cell. The masters
reading/writing from/to the memory are AXI complaint.
LPDDR2 MC follows the JESD209-2F specifications. It can
also be configured to power down and deep power down
modes.
There are 32 read/write AXI masters, the 33rd
master
is the host AXI master.
The host will configure all the registers, and the
device initialization of the memory will take place and
then the actual read/write operation will happen. The
buffer space will store all the master requests like
address, data and control information, the arbiter will
arbitrate the different master requests and gives grant to
one master. The command generation will issue different
commands to the memory like activate, read, write,
International Journal of Computer Applications Technology and Research
Volume 3– Issue 6, 390 - 394, 2014
www.ijcat.com 391
precharge, refresh, power down, deep power down which
is in synchronization with the refresh and timing control
block.
In this paper the LPDDR2 MC Supports SDRAM S2
and S4 devices which can be configured to 4 or 8 banks,
and the capacity is 64Mb to 8 GB. The operating
frequency of the memory is between 100 MHz to
533MHz.
This paper descries about the “Refresh And Timing
Controller Unit” which is part of Memory controller and
performs three important operations:
 Device initialization of memory device
 Refresh Control of memory device
 Timing Control for various memory related
command.
2. TOP MODULE OF REFRESH AND
TIMING CONTROLLER UNIT
Figure 2: Top module of “Refresh And Timing
Controller” unit for LPDDR2 memory controller
See Figure 2 the top module of the “Refresh And Timing
Controller” unit for LPDDR2 memory controller , the left
side signals which are input to “Refresh And Timing “block
from the Registers, Arbiter and Command Generator. The
right side signals which are output from “Refresh And
Timing “ block to the Memory, Registers and Command
Generator.
There are 5 input from registers are: cfg_reg[31:0],
cfg_reg_tb_cg[7:0],TACT[31:0],TPWR[31:0],TREF[31:0],PR
EF [31:0] ,3 inputs from command generator:
bk_act_cmg_rtb(8signals),pre_cmg_rtb(8signsls),prab_cmg_rtb
(1signal) , 1 input from arbiter: no_opn_row_arb_rtb and1 CKE
output to memory,4 output to register wen_tb,
addr_tb[8:0],din_tb[31:0],cfg_reg_tb_cg_in[7:0],
8 different output to command generator
acts_bk_rtb_cmg(8signal),actd_bk_rtb_cmg(8signal),rcd_rtb_c
mg(8signal),ras_rtb_cmg(8signal),pre_bp_rtb_cmg(8signal),rpa
b_rtb_cmg,po_ref_rtb_cmg[12:0].
3. IMPLEMENTATION OF REFRESH
AND TIMING CONTROLLER UNIT
3.1 Device initialization of memory device
FSM
Figure 3: Device initialization of memory device
FSM
See Figure 3 initialization of memory device FSM.
First step in device initialization is power ramp duration
minimum 50us (Ta state).Beginning (Tb State), CKE remain
low for at least 100 ns. After which it is asserted high. Clock
is stable at least 5 x tCK prior to the first low to high
transition of CKE. While keeping CKE high, NOP commands
(Tc state) is issued for at least 200 us. .After 200us is
satisfied, a MRW (Reset Td-state) command is issued at least
1us is waited, while keeping CKE asserted. After 1us is
satisfied(Te state) the MRR command is issued to poll the
DAI-bit to acknowledge when Device Auto-Initialization is
complete or the memory controller will wait for a minimum of
10us before proceeding. MRW commands is used to properly
configure the memory. The LPDDR2 device will now be in
IDLE state and ready for any valid command.
International Journal of Computer Applications Technology and Research
Volume 3– Issue 6, 390 - 394, 2014
www.ijcat.com 392
3.2 Refresh Control of memory device
FSM
Figure4: Refresh Control of memory device FSM
See Figure 4 the refresh control of memory device FSM.
Once device initialization is over it goes from idle state to
refresh interval state(REFI state) in which refresh interval
duration is maintied,postpone refresh is incremented each
time when refresh interval is expired(PP state).When
maximum postpone is reached conditional refresh is issued
and refresh cycle duration is maintied(REFcab state)for
number of postponed refresh.when there is no open row(no
request from master to read/write) a conditional refrseh is
issued.Refresh ineterval,maximum postpone duration and
Refresh Cycle duuration is shown in below table 1for
different memory densities.
Table 1: LPDDR2-SX : Refresh Requirements By
different Device Density
3.3 Timing Control for various memory
related command
Timing control various memory related command like
activate, precharge ,power down, deep power down
commands related timing are maintained in refresh and timing
block. All timings which are maintained are listed in below
table 2
Table 2:Different timing parameters reqiurements
by different frequency
4. SIMULATION RESULTS
4.1 Simulation of Device initialization of
memory device as per figure1
Figure 5: shows device initialization is completed by setting
cfg_reg_tb_cg[0]=1(DI BIT IS SET)
DI-BIT IS
SET
International Journal of Computer Applications Technology and Research
Volume 3– Issue 6, 390 - 394, 2014
www.ijcat.com 393
4.2 Simulation of Refresh
Figure 6: shows conditional refresh is issued in open row
condition as per figure 3
Figure 7: shows conditional refresh (Cndref is set) is issued
when maximum pospone is reached as per figure 3
4.3 Simulation of Timing Control for
activate command
Figure 8: shows when activate command is issued and after
some duration read/write bit is set and now memory can go
read/write
5. CONCULSION
Device initialization of device are simulated as per JDEC
spec. All timing parameters for refresh all bank, activate,
precharge, power-down and deep power down command are
simulated as per JDEC spec..
6. ACKNOWLEDGEMENT
We sincerely thank the management of BNM Institute of
Technology, HOD of ECE department and the project
coordinator for the support given to us. We also thank the
design and verification engineers at Graphene for giving us
the internship opportunity at Graphene Semiconductor
Services Private limited and guiding us during our internship
there.
7. REFERENCES
[1] “An introduction to SDRAM and memory
controllers” by BENNY AKESSON.
[2] “Design and implementation of a memory
controller for Real Time Applications” by Markus
Ringhofer
[3] “JEDEC Low Power Double Data Rate (LPDDR2)
SDRAM Standard,” 209-2F, June 2013.
Specification (Rev2.0), ARM Inc.
[4] DDR RAM by Gene Cooperman
[5] “Mobile LPDDR2 SDRAM „by Micron
technologies, 2010.
Cndref
is set
Oprow
=1
Cndref
is set
Activate
O/P
R/W is
International Journal of Computer Applications Technology and Research
Volume 3– Issue 6, 390 - 394, 2014
www.ijcat.com 394
[6] ”Verilog HDL, A Guide to Digital Design and
Synthesis” by Samir Palnitkar, 2nd edition.

Contenu connexe

Tendances

UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...
UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...
UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...shaotao liu
 
International Journal of Engineering Research and Development
International Journal of Engineering Research and DevelopmentInternational Journal of Engineering Research and Development
International Journal of Engineering Research and DevelopmentIJERD Editor
 
7SR191 Capa Protection Relays
7SR191 Capa Protection Relays7SR191 Capa Protection Relays
7SR191 Capa Protection Relaysashwini reliserv
 
Low-Power Design and Verification
Low-Power Design and VerificationLow-Power Design and Verification
Low-Power Design and VerificationDVClub
 
Design of subthreshold dml logic gates with power gating techniques
Design of subthreshold dml logic gates with power gating techniquesDesign of subthreshold dml logic gates with power gating techniques
Design of subthreshold dml logic gates with power gating techniqueseSAT Publishing House
 
Embedded programming in RTOS VxWorks for PROFIBUS VME interface card
Embedded programming in RTOS VxWorks for PROFIBUS VME interface cardEmbedded programming in RTOS VxWorks for PROFIBUS VME interface card
Embedded programming in RTOS VxWorks for PROFIBUS VME interface cardRinku Chandolia
 
Track d more performance less power - freescale final
Track d   more performance less power  - freescale finalTrack d   more performance less power  - freescale final
Track d more performance less power - freescale finalchiportal
 
SPICE LEVEL I/LEVEL II/LEVEL III AND BSIM MODELS
SPICE LEVEL I/LEVEL II/LEVEL III AND BSIM MODELSSPICE LEVEL I/LEVEL II/LEVEL III AND BSIM MODELS
SPICE LEVEL I/LEVEL II/LEVEL III AND BSIM MODELSPraveen Kumar
 
Fpga based motor controller
Fpga based motor controllerFpga based motor controller
Fpga based motor controllerUday Wankar
 
Architectural Level Techniques
Architectural Level TechniquesArchitectural Level Techniques
Architectural Level TechniquesGargiKhanna1
 
Simulation power analysis low power vlsi
Simulation power analysis   low power vlsiSimulation power analysis   low power vlsi
Simulation power analysis low power vlsiGargiKhanna1
 
Real Time Clock Interfacing with FPGA
Real Time Clock Interfacing with FPGAReal Time Clock Interfacing with FPGA
Real Time Clock Interfacing with FPGAMafaz Ahmed
 
Low power reduced instruction set architecture using clock gating technique
Low power reduced instruction set architecture using clock gating techniqueLow power reduced instruction set architecture using clock gating technique
Low power reduced instruction set architecture using clock gating techniqueVLSICS Design
 
Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Ashwin Shroff
 
A Novel Fuzzy Variable-Band Hysteresis Current Controller For Shunt Active Po...
A Novel Fuzzy Variable-Band Hysteresis Current Controller For Shunt Active Po...A Novel Fuzzy Variable-Band Hysteresis Current Controller For Shunt Active Po...
A Novel Fuzzy Variable-Band Hysteresis Current Controller For Shunt Active Po...IDES Editor
 
Library Characterization Flow
Library Characterization FlowLibrary Characterization Flow
Library Characterization FlowSatish Grandhi
 
D041121722
D041121722D041121722
D041121722IOSR-JEN
 

Tendances (20)

UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...
UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...
UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...
 
sirishamadishetty
sirishamadishettysirishamadishetty
sirishamadishetty
 
International Journal of Engineering Research and Development
International Journal of Engineering Research and DevelopmentInternational Journal of Engineering Research and Development
International Journal of Engineering Research and Development
 
7SR191 Capa Protection Relays
7SR191 Capa Protection Relays7SR191 Capa Protection Relays
7SR191 Capa Protection Relays
 
Low-Power Design and Verification
Low-Power Design and VerificationLow-Power Design and Verification
Low-Power Design and Verification
 
Design of subthreshold dml logic gates with power gating techniques
Design of subthreshold dml logic gates with power gating techniquesDesign of subthreshold dml logic gates with power gating techniques
Design of subthreshold dml logic gates with power gating techniques
 
Embedded programming in RTOS VxWorks for PROFIBUS VME interface card
Embedded programming in RTOS VxWorks for PROFIBUS VME interface cardEmbedded programming in RTOS VxWorks for PROFIBUS VME interface card
Embedded programming in RTOS VxWorks for PROFIBUS VME interface card
 
Track d more performance less power - freescale final
Track d   more performance less power  - freescale finalTrack d   more performance less power  - freescale final
Track d more performance less power - freescale final
 
SPICE LEVEL I/LEVEL II/LEVEL III AND BSIM MODELS
SPICE LEVEL I/LEVEL II/LEVEL III AND BSIM MODELSSPICE LEVEL I/LEVEL II/LEVEL III AND BSIM MODELS
SPICE LEVEL I/LEVEL II/LEVEL III AND BSIM MODELS
 
Ijeet 06 08_008
Ijeet 06 08_008Ijeet 06 08_008
Ijeet 06 08_008
 
Fpga based motor controller
Fpga based motor controllerFpga based motor controller
Fpga based motor controller
 
Architectural Level Techniques
Architectural Level TechniquesArchitectural Level Techniques
Architectural Level Techniques
 
Simulation power analysis low power vlsi
Simulation power analysis   low power vlsiSimulation power analysis   low power vlsi
Simulation power analysis low power vlsi
 
Real Time Clock Interfacing with FPGA
Real Time Clock Interfacing with FPGAReal Time Clock Interfacing with FPGA
Real Time Clock Interfacing with FPGA
 
Low power reduced instruction set architecture using clock gating technique
Low power reduced instruction set architecture using clock gating techniqueLow power reduced instruction set architecture using clock gating technique
Low power reduced instruction set architecture using clock gating technique
 
Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)
 
A Novel Fuzzy Variable-Band Hysteresis Current Controller For Shunt Active Po...
A Novel Fuzzy Variable-Band Hysteresis Current Controller For Shunt Active Po...A Novel Fuzzy Variable-Band Hysteresis Current Controller For Shunt Active Po...
A Novel Fuzzy Variable-Band Hysteresis Current Controller For Shunt Active Po...
 
Library Characterization Flow
Library Characterization FlowLibrary Characterization Flow
Library Characterization Flow
 
D041121722
D041121722D041121722
D041121722
 
Eh24847850
Eh24847850Eh24847850
Eh24847850
 

En vedette

Knowledge Management in the Cloud: Benefits and Risks
Knowledge Management in the Cloud: Benefits and RisksKnowledge Management in the Cloud: Benefits and Risks
Knowledge Management in the Cloud: Benefits and RisksEditor IJCATR
 
Dynamic Chunks Distribution Scheme for Multiservice Load Balancing Using Fibo...
Dynamic Chunks Distribution Scheme for Multiservice Load Balancing Using Fibo...Dynamic Chunks Distribution Scheme for Multiservice Load Balancing Using Fibo...
Dynamic Chunks Distribution Scheme for Multiservice Load Balancing Using Fibo...Editor IJCATR
 
Particle Swarm Optimization for Gene cluster Identification
Particle Swarm Optimization for Gene cluster IdentificationParticle Swarm Optimization for Gene cluster Identification
Particle Swarm Optimization for Gene cluster IdentificationEditor IJCATR
 
RED: A HIGH LINK UTILIZATION AND FAIR ALGORITHM
RED: A HIGH LINK UTILIZATION AND FAIR ALGORITHMRED: A HIGH LINK UTILIZATION AND FAIR ALGORITHM
RED: A HIGH LINK UTILIZATION AND FAIR ALGORITHMEditor IJCATR
 
Enhanced Detection System for Trust Aware P2P Communication Networks
Enhanced Detection System for Trust Aware P2P Communication NetworksEnhanced Detection System for Trust Aware P2P Communication Networks
Enhanced Detection System for Trust Aware P2P Communication NetworksEditor IJCATR
 
A Review on Classification Based Approaches for STEGanalysis Detection
A Review on Classification Based Approaches for STEGanalysis DetectionA Review on Classification Based Approaches for STEGanalysis Detection
A Review on Classification Based Approaches for STEGanalysis DetectionEditor IJCATR
 
BRAIN MACHINE INTERFACE SYSTEM FOR PERSON WITH QUADRIPLEGIA DISEASE
BRAIN MACHINE INTERFACE SYSTEM FOR PERSON WITH QUADRIPLEGIA DISEASEBRAIN MACHINE INTERFACE SYSTEM FOR PERSON WITH QUADRIPLEGIA DISEASE
BRAIN MACHINE INTERFACE SYSTEM FOR PERSON WITH QUADRIPLEGIA DISEASEEditor IJCATR
 
Assistive System Using Eye Gaze Estimation for Amyotrophic Lateral Sclerosis ...
Assistive System Using Eye Gaze Estimation for Amyotrophic Lateral Sclerosis ...Assistive System Using Eye Gaze Estimation for Amyotrophic Lateral Sclerosis ...
Assistive System Using Eye Gaze Estimation for Amyotrophic Lateral Sclerosis ...Editor IJCATR
 

En vedette (8)

Knowledge Management in the Cloud: Benefits and Risks
Knowledge Management in the Cloud: Benefits and RisksKnowledge Management in the Cloud: Benefits and Risks
Knowledge Management in the Cloud: Benefits and Risks
 
Dynamic Chunks Distribution Scheme for Multiservice Load Balancing Using Fibo...
Dynamic Chunks Distribution Scheme for Multiservice Load Balancing Using Fibo...Dynamic Chunks Distribution Scheme for Multiservice Load Balancing Using Fibo...
Dynamic Chunks Distribution Scheme for Multiservice Load Balancing Using Fibo...
 
Particle Swarm Optimization for Gene cluster Identification
Particle Swarm Optimization for Gene cluster IdentificationParticle Swarm Optimization for Gene cluster Identification
Particle Swarm Optimization for Gene cluster Identification
 
RED: A HIGH LINK UTILIZATION AND FAIR ALGORITHM
RED: A HIGH LINK UTILIZATION AND FAIR ALGORITHMRED: A HIGH LINK UTILIZATION AND FAIR ALGORITHM
RED: A HIGH LINK UTILIZATION AND FAIR ALGORITHM
 
Enhanced Detection System for Trust Aware P2P Communication Networks
Enhanced Detection System for Trust Aware P2P Communication NetworksEnhanced Detection System for Trust Aware P2P Communication Networks
Enhanced Detection System for Trust Aware P2P Communication Networks
 
A Review on Classification Based Approaches for STEGanalysis Detection
A Review on Classification Based Approaches for STEGanalysis DetectionA Review on Classification Based Approaches for STEGanalysis Detection
A Review on Classification Based Approaches for STEGanalysis Detection
 
BRAIN MACHINE INTERFACE SYSTEM FOR PERSON WITH QUADRIPLEGIA DISEASE
BRAIN MACHINE INTERFACE SYSTEM FOR PERSON WITH QUADRIPLEGIA DISEASEBRAIN MACHINE INTERFACE SYSTEM FOR PERSON WITH QUADRIPLEGIA DISEASE
BRAIN MACHINE INTERFACE SYSTEM FOR PERSON WITH QUADRIPLEGIA DISEASE
 
Assistive System Using Eye Gaze Estimation for Amyotrophic Lateral Sclerosis ...
Assistive System Using Eye Gaze Estimation for Amyotrophic Lateral Sclerosis ...Assistive System Using Eye Gaze Estimation for Amyotrophic Lateral Sclerosis ...
Assistive System Using Eye Gaze Estimation for Amyotrophic Lateral Sclerosis ...
 

Similaire à Design and Implementation of Refresh and Timing Controller Unit for LPDDR2 Memory Controller

Modeling of DDR4 Memory and Advanced Verifications of DDR4 Memory Subsystem
Modeling of DDR4 Memory and Advanced Verifications of DDR4 Memory SubsystemModeling of DDR4 Memory and Advanced Verifications of DDR4 Memory Subsystem
Modeling of DDR4 Memory and Advanced Verifications of DDR4 Memory SubsystemIRJET Journal
 
Processor Management
Processor ManagementProcessor Management
Processor ManagementSumit kumar
 
3 design
3 design3 design
3 designhanmya
 
Hardware
HardwareHardware
HardwareMuuluu
 
International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)IJERD Editor
 
Real Time Atomization of agriculture system for the modernization of indian a...
Real Time Atomization of agriculture system for the modernization of indian a...Real Time Atomization of agriculture system for the modernization of indian a...
Real Time Atomization of agriculture system for the modernization of indian a...SHAMEER C M
 
Real time atomization of agriculture system for the modernization of indian a...
Real time atomization of agriculture system for the modernization of indian a...Real time atomization of agriculture system for the modernization of indian a...
Real time atomization of agriculture system for the modernization of indian a...SHAMEER C M
 
computer organization and architecture notes
computer organization and architecture notescomputer organization and architecture notes
computer organization and architecture notesUpasana Talukdar
 
INDUSTRIAL TRAINING REPORT EMBEDDED SYSTEM.pptx
INDUSTRIAL TRAINING REPORT EMBEDDED SYSTEM.pptxINDUSTRIAL TRAINING REPORT EMBEDDED SYSTEM.pptx
INDUSTRIAL TRAINING REPORT EMBEDDED SYSTEM.pptxMeghdeepSingh
 
Bca examination 2015 csa
Bca examination 2015 csaBca examination 2015 csa
Bca examination 2015 csaAnjaan Gajendra
 
Advantages And Disadvantages Of Microcontroller
Advantages And Disadvantages Of MicrocontrollerAdvantages And Disadvantages Of Microcontroller
Advantages And Disadvantages Of MicrocontrollerKara Liu
 
summary intel spec for "msr reg" memory order
summary intel spec for "msr reg" memory ordersummary intel spec for "msr reg" memory order
summary intel spec for "msr reg" memory ordersuddentrike2
 

Similaire à Design and Implementation of Refresh and Timing Controller Unit for LPDDR2 Memory Controller (20)

PowerManagement
PowerManagementPowerManagement
PowerManagement
 
Arm7 architecture
Arm7 architectureArm7 architecture
Arm7 architecture
 
Modeling of DDR4 Memory and Advanced Verifications of DDR4 Memory Subsystem
Modeling of DDR4 Memory and Advanced Verifications of DDR4 Memory SubsystemModeling of DDR4 Memory and Advanced Verifications of DDR4 Memory Subsystem
Modeling of DDR4 Memory and Advanced Verifications of DDR4 Memory Subsystem
 
Matter new
Matter newMatter new
Matter new
 
Processor Management
Processor ManagementProcessor Management
Processor Management
 
3 design
3 design3 design
3 design
 
Hardware
HardwareHardware
Hardware
 
International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)
 
1.2 Worksheet 1.pptx
1.2 Worksheet 1.pptx1.2 Worksheet 1.pptx
1.2 Worksheet 1.pptx
 
Real Time Atomization of agriculture system for the modernization of indian a...
Real Time Atomization of agriculture system for the modernization of indian a...Real Time Atomization of agriculture system for the modernization of indian a...
Real Time Atomization of agriculture system for the modernization of indian a...
 
Real time atomization of agriculture system for the modernization of indian a...
Real time atomization of agriculture system for the modernization of indian a...Real time atomization of agriculture system for the modernization of indian a...
Real time atomization of agriculture system for the modernization of indian a...
 
computer organization and architecture notes
computer organization and architecture notescomputer organization and architecture notes
computer organization and architecture notes
 
Mod3
Mod3Mod3
Mod3
 
2.computer org.
2.computer org.2.computer org.
2.computer org.
 
BODY
BODYBODY
BODY
 
INDUSTRIAL TRAINING REPORT EMBEDDED SYSTEM.pptx
INDUSTRIAL TRAINING REPORT EMBEDDED SYSTEM.pptxINDUSTRIAL TRAINING REPORT EMBEDDED SYSTEM.pptx
INDUSTRIAL TRAINING REPORT EMBEDDED SYSTEM.pptx
 
Bca examination 2015 csa
Bca examination 2015 csaBca examination 2015 csa
Bca examination 2015 csa
 
Advantages And Disadvantages Of Microcontroller
Advantages And Disadvantages Of MicrocontrollerAdvantages And Disadvantages Of Microcontroller
Advantages And Disadvantages Of Microcontroller
 
summary intel spec for "msr reg" memory order
summary intel spec for "msr reg" memory ordersummary intel spec for "msr reg" memory order
summary intel spec for "msr reg" memory order
 
presentation on SCB,DEBUG,RESET of Arm Cortex processor
presentation on SCB,DEBUG,RESET of Arm Cortex processorpresentation on SCB,DEBUG,RESET of Arm Cortex processor
presentation on SCB,DEBUG,RESET of Arm Cortex processor
 

Plus de Editor IJCATR

Text Mining in Digital Libraries using OKAPI BM25 Model
 Text Mining in Digital Libraries using OKAPI BM25 Model Text Mining in Digital Libraries using OKAPI BM25 Model
Text Mining in Digital Libraries using OKAPI BM25 ModelEditor IJCATR
 
Green Computing, eco trends, climate change, e-waste and eco-friendly
Green Computing, eco trends, climate change, e-waste and eco-friendlyGreen Computing, eco trends, climate change, e-waste and eco-friendly
Green Computing, eco trends, climate change, e-waste and eco-friendlyEditor IJCATR
 
Policies for Green Computing and E-Waste in Nigeria
 Policies for Green Computing and E-Waste in Nigeria Policies for Green Computing and E-Waste in Nigeria
Policies for Green Computing and E-Waste in NigeriaEditor IJCATR
 
Performance Evaluation of VANETs for Evaluating Node Stability in Dynamic Sce...
Performance Evaluation of VANETs for Evaluating Node Stability in Dynamic Sce...Performance Evaluation of VANETs for Evaluating Node Stability in Dynamic Sce...
Performance Evaluation of VANETs for Evaluating Node Stability in Dynamic Sce...Editor IJCATR
 
Optimum Location of DG Units Considering Operation Conditions
Optimum Location of DG Units Considering Operation ConditionsOptimum Location of DG Units Considering Operation Conditions
Optimum Location of DG Units Considering Operation ConditionsEditor IJCATR
 
Analysis of Comparison of Fuzzy Knn, C4.5 Algorithm, and Naïve Bayes Classifi...
Analysis of Comparison of Fuzzy Knn, C4.5 Algorithm, and Naïve Bayes Classifi...Analysis of Comparison of Fuzzy Knn, C4.5 Algorithm, and Naïve Bayes Classifi...
Analysis of Comparison of Fuzzy Knn, C4.5 Algorithm, and Naïve Bayes Classifi...Editor IJCATR
 
Evaluating Semantic Similarity between Biomedical Concepts/Classes through S...
 Evaluating Semantic Similarity between Biomedical Concepts/Classes through S... Evaluating Semantic Similarity between Biomedical Concepts/Classes through S...
Evaluating Semantic Similarity between Biomedical Concepts/Classes through S...Editor IJCATR
 
Semantic Similarity Measures between Terms in the Biomedical Domain within f...
 Semantic Similarity Measures between Terms in the Biomedical Domain within f... Semantic Similarity Measures between Terms in the Biomedical Domain within f...
Semantic Similarity Measures between Terms in the Biomedical Domain within f...Editor IJCATR
 
A Strategy for Improving the Performance of Small Files in Openstack Swift
 A Strategy for Improving the Performance of Small Files in Openstack Swift  A Strategy for Improving the Performance of Small Files in Openstack Swift
A Strategy for Improving the Performance of Small Files in Openstack Swift Editor IJCATR
 
Integrated System for Vehicle Clearance and Registration
Integrated System for Vehicle Clearance and RegistrationIntegrated System for Vehicle Clearance and Registration
Integrated System for Vehicle Clearance and RegistrationEditor IJCATR
 
Assessment of the Efficiency of Customer Order Management System: A Case Stu...
 Assessment of the Efficiency of Customer Order Management System: A Case Stu... Assessment of the Efficiency of Customer Order Management System: A Case Stu...
Assessment of the Efficiency of Customer Order Management System: A Case Stu...Editor IJCATR
 
Energy-Aware Routing in Wireless Sensor Network Using Modified Bi-Directional A*
Energy-Aware Routing in Wireless Sensor Network Using Modified Bi-Directional A*Energy-Aware Routing in Wireless Sensor Network Using Modified Bi-Directional A*
Energy-Aware Routing in Wireless Sensor Network Using Modified Bi-Directional A*Editor IJCATR
 
Security in Software Defined Networks (SDN): Challenges and Research Opportun...
Security in Software Defined Networks (SDN): Challenges and Research Opportun...Security in Software Defined Networks (SDN): Challenges and Research Opportun...
Security in Software Defined Networks (SDN): Challenges and Research Opportun...Editor IJCATR
 
Measure the Similarity of Complaint Document Using Cosine Similarity Based on...
Measure the Similarity of Complaint Document Using Cosine Similarity Based on...Measure the Similarity of Complaint Document Using Cosine Similarity Based on...
Measure the Similarity of Complaint Document Using Cosine Similarity Based on...Editor IJCATR
 
Hangul Recognition Using Support Vector Machine
Hangul Recognition Using Support Vector MachineHangul Recognition Using Support Vector Machine
Hangul Recognition Using Support Vector MachineEditor IJCATR
 
Application of 3D Printing in Education
Application of 3D Printing in EducationApplication of 3D Printing in Education
Application of 3D Printing in EducationEditor IJCATR
 
Survey on Energy-Efficient Routing Algorithms for Underwater Wireless Sensor ...
Survey on Energy-Efficient Routing Algorithms for Underwater Wireless Sensor ...Survey on Energy-Efficient Routing Algorithms for Underwater Wireless Sensor ...
Survey on Energy-Efficient Routing Algorithms for Underwater Wireless Sensor ...Editor IJCATR
 
Comparative analysis on Void Node Removal Routing algorithms for Underwater W...
Comparative analysis on Void Node Removal Routing algorithms for Underwater W...Comparative analysis on Void Node Removal Routing algorithms for Underwater W...
Comparative analysis on Void Node Removal Routing algorithms for Underwater W...Editor IJCATR
 
Decay Property for Solutions to Plate Type Equations with Variable Coefficients
Decay Property for Solutions to Plate Type Equations with Variable CoefficientsDecay Property for Solutions to Plate Type Equations with Variable Coefficients
Decay Property for Solutions to Plate Type Equations with Variable CoefficientsEditor IJCATR
 
Prediction of Heart Disease in Diabetic patients using Naive Bayes Classifica...
Prediction of Heart Disease in Diabetic patients using Naive Bayes Classifica...Prediction of Heart Disease in Diabetic patients using Naive Bayes Classifica...
Prediction of Heart Disease in Diabetic patients using Naive Bayes Classifica...Editor IJCATR
 

Plus de Editor IJCATR (20)

Text Mining in Digital Libraries using OKAPI BM25 Model
 Text Mining in Digital Libraries using OKAPI BM25 Model Text Mining in Digital Libraries using OKAPI BM25 Model
Text Mining in Digital Libraries using OKAPI BM25 Model
 
Green Computing, eco trends, climate change, e-waste and eco-friendly
Green Computing, eco trends, climate change, e-waste and eco-friendlyGreen Computing, eco trends, climate change, e-waste and eco-friendly
Green Computing, eco trends, climate change, e-waste and eco-friendly
 
Policies for Green Computing and E-Waste in Nigeria
 Policies for Green Computing and E-Waste in Nigeria Policies for Green Computing and E-Waste in Nigeria
Policies for Green Computing and E-Waste in Nigeria
 
Performance Evaluation of VANETs for Evaluating Node Stability in Dynamic Sce...
Performance Evaluation of VANETs for Evaluating Node Stability in Dynamic Sce...Performance Evaluation of VANETs for Evaluating Node Stability in Dynamic Sce...
Performance Evaluation of VANETs for Evaluating Node Stability in Dynamic Sce...
 
Optimum Location of DG Units Considering Operation Conditions
Optimum Location of DG Units Considering Operation ConditionsOptimum Location of DG Units Considering Operation Conditions
Optimum Location of DG Units Considering Operation Conditions
 
Analysis of Comparison of Fuzzy Knn, C4.5 Algorithm, and Naïve Bayes Classifi...
Analysis of Comparison of Fuzzy Knn, C4.5 Algorithm, and Naïve Bayes Classifi...Analysis of Comparison of Fuzzy Knn, C4.5 Algorithm, and Naïve Bayes Classifi...
Analysis of Comparison of Fuzzy Knn, C4.5 Algorithm, and Naïve Bayes Classifi...
 
Evaluating Semantic Similarity between Biomedical Concepts/Classes through S...
 Evaluating Semantic Similarity between Biomedical Concepts/Classes through S... Evaluating Semantic Similarity between Biomedical Concepts/Classes through S...
Evaluating Semantic Similarity between Biomedical Concepts/Classes through S...
 
Semantic Similarity Measures between Terms in the Biomedical Domain within f...
 Semantic Similarity Measures between Terms in the Biomedical Domain within f... Semantic Similarity Measures between Terms in the Biomedical Domain within f...
Semantic Similarity Measures between Terms in the Biomedical Domain within f...
 
A Strategy for Improving the Performance of Small Files in Openstack Swift
 A Strategy for Improving the Performance of Small Files in Openstack Swift  A Strategy for Improving the Performance of Small Files in Openstack Swift
A Strategy for Improving the Performance of Small Files in Openstack Swift
 
Integrated System for Vehicle Clearance and Registration
Integrated System for Vehicle Clearance and RegistrationIntegrated System for Vehicle Clearance and Registration
Integrated System for Vehicle Clearance and Registration
 
Assessment of the Efficiency of Customer Order Management System: A Case Stu...
 Assessment of the Efficiency of Customer Order Management System: A Case Stu... Assessment of the Efficiency of Customer Order Management System: A Case Stu...
Assessment of the Efficiency of Customer Order Management System: A Case Stu...
 
Energy-Aware Routing in Wireless Sensor Network Using Modified Bi-Directional A*
Energy-Aware Routing in Wireless Sensor Network Using Modified Bi-Directional A*Energy-Aware Routing in Wireless Sensor Network Using Modified Bi-Directional A*
Energy-Aware Routing in Wireless Sensor Network Using Modified Bi-Directional A*
 
Security in Software Defined Networks (SDN): Challenges and Research Opportun...
Security in Software Defined Networks (SDN): Challenges and Research Opportun...Security in Software Defined Networks (SDN): Challenges and Research Opportun...
Security in Software Defined Networks (SDN): Challenges and Research Opportun...
 
Measure the Similarity of Complaint Document Using Cosine Similarity Based on...
Measure the Similarity of Complaint Document Using Cosine Similarity Based on...Measure the Similarity of Complaint Document Using Cosine Similarity Based on...
Measure the Similarity of Complaint Document Using Cosine Similarity Based on...
 
Hangul Recognition Using Support Vector Machine
Hangul Recognition Using Support Vector MachineHangul Recognition Using Support Vector Machine
Hangul Recognition Using Support Vector Machine
 
Application of 3D Printing in Education
Application of 3D Printing in EducationApplication of 3D Printing in Education
Application of 3D Printing in Education
 
Survey on Energy-Efficient Routing Algorithms for Underwater Wireless Sensor ...
Survey on Energy-Efficient Routing Algorithms for Underwater Wireless Sensor ...Survey on Energy-Efficient Routing Algorithms for Underwater Wireless Sensor ...
Survey on Energy-Efficient Routing Algorithms for Underwater Wireless Sensor ...
 
Comparative analysis on Void Node Removal Routing algorithms for Underwater W...
Comparative analysis on Void Node Removal Routing algorithms for Underwater W...Comparative analysis on Void Node Removal Routing algorithms for Underwater W...
Comparative analysis on Void Node Removal Routing algorithms for Underwater W...
 
Decay Property for Solutions to Plate Type Equations with Variable Coefficients
Decay Property for Solutions to Plate Type Equations with Variable CoefficientsDecay Property for Solutions to Plate Type Equations with Variable Coefficients
Decay Property for Solutions to Plate Type Equations with Variable Coefficients
 
Prediction of Heart Disease in Diabetic patients using Naive Bayes Classifica...
Prediction of Heart Disease in Diabetic patients using Naive Bayes Classifica...Prediction of Heart Disease in Diabetic patients using Naive Bayes Classifica...
Prediction of Heart Disease in Diabetic patients using Naive Bayes Classifica...
 

Dernier

activity_diagram_combine_v4_20190827.pdfactivity_diagram_combine_v4_20190827.pdf
activity_diagram_combine_v4_20190827.pdfactivity_diagram_combine_v4_20190827.pdfactivity_diagram_combine_v4_20190827.pdfactivity_diagram_combine_v4_20190827.pdf
activity_diagram_combine_v4_20190827.pdfactivity_diagram_combine_v4_20190827.pdfJamie (Taka) Wang
 
20230202 - Introduction to tis-py
20230202 - Introduction to tis-py20230202 - Introduction to tis-py
20230202 - Introduction to tis-pyJamie (Taka) Wang
 
Secure your environment with UiPath and CyberArk technologies - Session 1
Secure your environment with UiPath and CyberArk technologies - Session 1Secure your environment with UiPath and CyberArk technologies - Session 1
Secure your environment with UiPath and CyberArk technologies - Session 1DianaGray10
 
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...Aggregage
 
Apres-Cyber - The Data Dilemma: Bridging Offensive Operations and Machine Lea...
Apres-Cyber - The Data Dilemma: Bridging Offensive Operations and Machine Lea...Apres-Cyber - The Data Dilemma: Bridging Offensive Operations and Machine Lea...
Apres-Cyber - The Data Dilemma: Bridging Offensive Operations and Machine Lea...Will Schroeder
 
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve Decarbonization
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve DecarbonizationUsing IESVE for Loads, Sizing and Heat Pump Modeling to Achieve Decarbonization
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve DecarbonizationIES VE
 
Machine Learning Model Validation (Aijun Zhang 2024).pdf
Machine Learning Model Validation (Aijun Zhang 2024).pdfMachine Learning Model Validation (Aijun Zhang 2024).pdf
Machine Learning Model Validation (Aijun Zhang 2024).pdfAijun Zhang
 
Basic Building Blocks of Internet of Things.
Basic Building Blocks of Internet of Things.Basic Building Blocks of Internet of Things.
Basic Building Blocks of Internet of Things.YounusS2
 
Connector Corner: Extending LLM automation use cases with UiPath GenAI connec...
Connector Corner: Extending LLM automation use cases with UiPath GenAI connec...Connector Corner: Extending LLM automation use cases with UiPath GenAI connec...
Connector Corner: Extending LLM automation use cases with UiPath GenAI connec...DianaGray10
 
VoIP Service and Marketing using Odoo and Asterisk PBX
VoIP Service and Marketing using Odoo and Asterisk PBXVoIP Service and Marketing using Odoo and Asterisk PBX
VoIP Service and Marketing using Odoo and Asterisk PBXTarek Kalaji
 
UiPath Community: AI for UiPath Automation Developers
UiPath Community: AI for UiPath Automation DevelopersUiPath Community: AI for UiPath Automation Developers
UiPath Community: AI for UiPath Automation DevelopersUiPathCommunity
 
Building Your Own AI Instance (TBLC AI )
Building Your Own AI Instance (TBLC AI )Building Your Own AI Instance (TBLC AI )
Building Your Own AI Instance (TBLC AI )Brian Pichman
 
Crea il tuo assistente AI con lo Stregatto (open source python framework)
Crea il tuo assistente AI con lo Stregatto (open source python framework)Crea il tuo assistente AI con lo Stregatto (open source python framework)
Crea il tuo assistente AI con lo Stregatto (open source python framework)Commit University
 
Bird eye's view on Camunda open source ecosystem
Bird eye's view on Camunda open source ecosystemBird eye's view on Camunda open source ecosystem
Bird eye's view on Camunda open source ecosystemAsko Soukka
 
Meet the new FSP 3000 M-Flex800™
Meet the new FSP 3000 M-Flex800™Meet the new FSP 3000 M-Flex800™
Meet the new FSP 3000 M-Flex800™Adtran
 
Anypoint Code Builder , Google Pub sub connector and MuleSoft RPA
Anypoint Code Builder , Google Pub sub connector and MuleSoft RPAAnypoint Code Builder , Google Pub sub connector and MuleSoft RPA
Anypoint Code Builder , Google Pub sub connector and MuleSoft RPAshyamraj55
 
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdf
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdfUiPath Solutions Management Preview - Northern CA Chapter - March 22.pdf
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdfDianaGray10
 
Salesforce Miami User Group Event - 1st Quarter 2024
Salesforce Miami User Group Event - 1st Quarter 2024Salesforce Miami User Group Event - 1st Quarter 2024
Salesforce Miami User Group Event - 1st Quarter 2024SkyPlanner
 
IESVE Software for Florida Code Compliance Using ASHRAE 90.1-2019
IESVE Software for Florida Code Compliance Using ASHRAE 90.1-2019IESVE Software for Florida Code Compliance Using ASHRAE 90.1-2019
IESVE Software for Florida Code Compliance Using ASHRAE 90.1-2019IES VE
 

Dernier (20)

20230104 - machine vision
20230104 - machine vision20230104 - machine vision
20230104 - machine vision
 
activity_diagram_combine_v4_20190827.pdfactivity_diagram_combine_v4_20190827.pdf
activity_diagram_combine_v4_20190827.pdfactivity_diagram_combine_v4_20190827.pdfactivity_diagram_combine_v4_20190827.pdfactivity_diagram_combine_v4_20190827.pdf
activity_diagram_combine_v4_20190827.pdfactivity_diagram_combine_v4_20190827.pdf
 
20230202 - Introduction to tis-py
20230202 - Introduction to tis-py20230202 - Introduction to tis-py
20230202 - Introduction to tis-py
 
Secure your environment with UiPath and CyberArk technologies - Session 1
Secure your environment with UiPath and CyberArk technologies - Session 1Secure your environment with UiPath and CyberArk technologies - Session 1
Secure your environment with UiPath and CyberArk technologies - Session 1
 
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...
 
Apres-Cyber - The Data Dilemma: Bridging Offensive Operations and Machine Lea...
Apres-Cyber - The Data Dilemma: Bridging Offensive Operations and Machine Lea...Apres-Cyber - The Data Dilemma: Bridging Offensive Operations and Machine Lea...
Apres-Cyber - The Data Dilemma: Bridging Offensive Operations and Machine Lea...
 
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve Decarbonization
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve DecarbonizationUsing IESVE for Loads, Sizing and Heat Pump Modeling to Achieve Decarbonization
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve Decarbonization
 
Machine Learning Model Validation (Aijun Zhang 2024).pdf
Machine Learning Model Validation (Aijun Zhang 2024).pdfMachine Learning Model Validation (Aijun Zhang 2024).pdf
Machine Learning Model Validation (Aijun Zhang 2024).pdf
 
Basic Building Blocks of Internet of Things.
Basic Building Blocks of Internet of Things.Basic Building Blocks of Internet of Things.
Basic Building Blocks of Internet of Things.
 
Connector Corner: Extending LLM automation use cases with UiPath GenAI connec...
Connector Corner: Extending LLM automation use cases with UiPath GenAI connec...Connector Corner: Extending LLM automation use cases with UiPath GenAI connec...
Connector Corner: Extending LLM automation use cases with UiPath GenAI connec...
 
VoIP Service and Marketing using Odoo and Asterisk PBX
VoIP Service and Marketing using Odoo and Asterisk PBXVoIP Service and Marketing using Odoo and Asterisk PBX
VoIP Service and Marketing using Odoo and Asterisk PBX
 
UiPath Community: AI for UiPath Automation Developers
UiPath Community: AI for UiPath Automation DevelopersUiPath Community: AI for UiPath Automation Developers
UiPath Community: AI for UiPath Automation Developers
 
Building Your Own AI Instance (TBLC AI )
Building Your Own AI Instance (TBLC AI )Building Your Own AI Instance (TBLC AI )
Building Your Own AI Instance (TBLC AI )
 
Crea il tuo assistente AI con lo Stregatto (open source python framework)
Crea il tuo assistente AI con lo Stregatto (open source python framework)Crea il tuo assistente AI con lo Stregatto (open source python framework)
Crea il tuo assistente AI con lo Stregatto (open source python framework)
 
Bird eye's view on Camunda open source ecosystem
Bird eye's view on Camunda open source ecosystemBird eye's view on Camunda open source ecosystem
Bird eye's view on Camunda open source ecosystem
 
Meet the new FSP 3000 M-Flex800™
Meet the new FSP 3000 M-Flex800™Meet the new FSP 3000 M-Flex800™
Meet the new FSP 3000 M-Flex800™
 
Anypoint Code Builder , Google Pub sub connector and MuleSoft RPA
Anypoint Code Builder , Google Pub sub connector and MuleSoft RPAAnypoint Code Builder , Google Pub sub connector and MuleSoft RPA
Anypoint Code Builder , Google Pub sub connector and MuleSoft RPA
 
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdf
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdfUiPath Solutions Management Preview - Northern CA Chapter - March 22.pdf
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdf
 
Salesforce Miami User Group Event - 1st Quarter 2024
Salesforce Miami User Group Event - 1st Quarter 2024Salesforce Miami User Group Event - 1st Quarter 2024
Salesforce Miami User Group Event - 1st Quarter 2024
 
IESVE Software for Florida Code Compliance Using ASHRAE 90.1-2019
IESVE Software for Florida Code Compliance Using ASHRAE 90.1-2019IESVE Software for Florida Code Compliance Using ASHRAE 90.1-2019
IESVE Software for Florida Code Compliance Using ASHRAE 90.1-2019
 

Design and Implementation of Refresh and Timing Controller Unit for LPDDR2 Memory Controller

  • 1. International Journal of Computer Applications Technology and Research Volume 3– Issue 6, 390 - 394, 2014 www.ijcat.com 390 Design and Implementation of Refresh and Timing Controller Unit for LPDDR2 Memory Controller Sandya M.J Dept. of Electronics and communication BNM Institute Of Technology Bangalore,India Chaitra .N Dept. of Electronics and communication BNM Institute Of Technology Bangalore,India Ramudu B Graphene Semiconductor India Pvt Ltd Bangalore,India Abstract: this paper presents a “Implementation of “Refresh And Timing Controller” unit for low power double data rate 2 memory controller (LPDDR2 MEMORY CONTROLLER). “Refresh and Timing Controller” unit plays a vital role for LPDDR2 memory controller .It maintains different timing parameters to handle various commands for memory like refresh, read and write operations and also performs Memory Initialization. Since it is low power DDR2 the maximum duration in power-down mode and deep power down mode is maintained by “Refresh and Timing Controller” unit. The refresh rate period is programmable using the Refresh Period Register. It supports “All Bank Refresh”. The unit has timers to accommodate Refresh, Read/Write, and Power down modes. The RTL is done using the System Verilog. The design is simulated Keywords: LPDDR2 MC; Design; Device initialization; Refresh requirement;Timing parameters 1. INTRODUCTION Embedded systems usually have a limited amount of memory available; this is because of cost, size, power, weight or other constraints imposed by the overall system requirements. It may be necessary to control how this memory is allocated so that it can be used effectively. Handheld device like mobile, tablet etc are battery operated. For long time battery lasting better power optimization is required in those devices. Nowadays the devices are having multiple masters and share common memory for their applications. LPDDR2 is better fit for these kinds of devices. LPDDR2 memories consume low power. LPDDR2 memory controller accepts write/read commands from multiple masters and generates memory related commands. Functions of memory controller are  solves different bandwidth requirement issues  handles the “refresh” cycle for Memory.  handles read and write operations with bank/row/column addressing. Since these memories are made with capacitors, charge will leak continuously so refreshing is required memory controller will generate refresh commands as specified in JEDEC specification. For each refresh in a LPDDR2 row, the stored information in each cell is read out and then written back to itself as each LPDDR2 bit read is self-destructive. The refresh process is inevitable for maintaining data correctness, unfortunately, at the expense of power and bandwidth overhead. This paper is organized as follows. The brief introduction to “Refresh And Timing Controller” “is given in section 2 describes top module of“ Refresh And Timing Controller”, section 3 describes the implementation of “Refresh And Timing Controller” for LPDDR2 memory controller. Section 4 describes the result and analysis. Figure 1: LPDDR2 Memory controller See figure 1 the LPDDR2 memory controller,LPDDR2 MC‟s are used to drive DDR2 SDRAM, where data is transferred on the rising and falling access of the memory clock of the system without increasing the clock rate or increasing the bus width to the memory cell. The masters reading/writing from/to the memory are AXI complaint. LPDDR2 MC follows the JESD209-2F specifications. It can also be configured to power down and deep power down modes. There are 32 read/write AXI masters, the 33rd master is the host AXI master. The host will configure all the registers, and the device initialization of the memory will take place and then the actual read/write operation will happen. The buffer space will store all the master requests like address, data and control information, the arbiter will arbitrate the different master requests and gives grant to one master. The command generation will issue different commands to the memory like activate, read, write,
  • 2. International Journal of Computer Applications Technology and Research Volume 3– Issue 6, 390 - 394, 2014 www.ijcat.com 391 precharge, refresh, power down, deep power down which is in synchronization with the refresh and timing control block. In this paper the LPDDR2 MC Supports SDRAM S2 and S4 devices which can be configured to 4 or 8 banks, and the capacity is 64Mb to 8 GB. The operating frequency of the memory is between 100 MHz to 533MHz. This paper descries about the “Refresh And Timing Controller Unit” which is part of Memory controller and performs three important operations:  Device initialization of memory device  Refresh Control of memory device  Timing Control for various memory related command. 2. TOP MODULE OF REFRESH AND TIMING CONTROLLER UNIT Figure 2: Top module of “Refresh And Timing Controller” unit for LPDDR2 memory controller See Figure 2 the top module of the “Refresh And Timing Controller” unit for LPDDR2 memory controller , the left side signals which are input to “Refresh And Timing “block from the Registers, Arbiter and Command Generator. The right side signals which are output from “Refresh And Timing “ block to the Memory, Registers and Command Generator. There are 5 input from registers are: cfg_reg[31:0], cfg_reg_tb_cg[7:0],TACT[31:0],TPWR[31:0],TREF[31:0],PR EF [31:0] ,3 inputs from command generator: bk_act_cmg_rtb(8signals),pre_cmg_rtb(8signsls),prab_cmg_rtb (1signal) , 1 input from arbiter: no_opn_row_arb_rtb and1 CKE output to memory,4 output to register wen_tb, addr_tb[8:0],din_tb[31:0],cfg_reg_tb_cg_in[7:0], 8 different output to command generator acts_bk_rtb_cmg(8signal),actd_bk_rtb_cmg(8signal),rcd_rtb_c mg(8signal),ras_rtb_cmg(8signal),pre_bp_rtb_cmg(8signal),rpa b_rtb_cmg,po_ref_rtb_cmg[12:0]. 3. IMPLEMENTATION OF REFRESH AND TIMING CONTROLLER UNIT 3.1 Device initialization of memory device FSM Figure 3: Device initialization of memory device FSM See Figure 3 initialization of memory device FSM. First step in device initialization is power ramp duration minimum 50us (Ta state).Beginning (Tb State), CKE remain low for at least 100 ns. After which it is asserted high. Clock is stable at least 5 x tCK prior to the first low to high transition of CKE. While keeping CKE high, NOP commands (Tc state) is issued for at least 200 us. .After 200us is satisfied, a MRW (Reset Td-state) command is issued at least 1us is waited, while keeping CKE asserted. After 1us is satisfied(Te state) the MRR command is issued to poll the DAI-bit to acknowledge when Device Auto-Initialization is complete or the memory controller will wait for a minimum of 10us before proceeding. MRW commands is used to properly configure the memory. The LPDDR2 device will now be in IDLE state and ready for any valid command.
  • 3. International Journal of Computer Applications Technology and Research Volume 3– Issue 6, 390 - 394, 2014 www.ijcat.com 392 3.2 Refresh Control of memory device FSM Figure4: Refresh Control of memory device FSM See Figure 4 the refresh control of memory device FSM. Once device initialization is over it goes from idle state to refresh interval state(REFI state) in which refresh interval duration is maintied,postpone refresh is incremented each time when refresh interval is expired(PP state).When maximum postpone is reached conditional refresh is issued and refresh cycle duration is maintied(REFcab state)for number of postponed refresh.when there is no open row(no request from master to read/write) a conditional refrseh is issued.Refresh ineterval,maximum postpone duration and Refresh Cycle duuration is shown in below table 1for different memory densities. Table 1: LPDDR2-SX : Refresh Requirements By different Device Density 3.3 Timing Control for various memory related command Timing control various memory related command like activate, precharge ,power down, deep power down commands related timing are maintained in refresh and timing block. All timings which are maintained are listed in below table 2 Table 2:Different timing parameters reqiurements by different frequency 4. SIMULATION RESULTS 4.1 Simulation of Device initialization of memory device as per figure1 Figure 5: shows device initialization is completed by setting cfg_reg_tb_cg[0]=1(DI BIT IS SET) DI-BIT IS SET
  • 4. International Journal of Computer Applications Technology and Research Volume 3– Issue 6, 390 - 394, 2014 www.ijcat.com 393 4.2 Simulation of Refresh Figure 6: shows conditional refresh is issued in open row condition as per figure 3 Figure 7: shows conditional refresh (Cndref is set) is issued when maximum pospone is reached as per figure 3 4.3 Simulation of Timing Control for activate command Figure 8: shows when activate command is issued and after some duration read/write bit is set and now memory can go read/write 5. CONCULSION Device initialization of device are simulated as per JDEC spec. All timing parameters for refresh all bank, activate, precharge, power-down and deep power down command are simulated as per JDEC spec.. 6. ACKNOWLEDGEMENT We sincerely thank the management of BNM Institute of Technology, HOD of ECE department and the project coordinator for the support given to us. We also thank the design and verification engineers at Graphene for giving us the internship opportunity at Graphene Semiconductor Services Private limited and guiding us during our internship there. 7. REFERENCES [1] “An introduction to SDRAM and memory controllers” by BENNY AKESSON. [2] “Design and implementation of a memory controller for Real Time Applications” by Markus Ringhofer [3] “JEDEC Low Power Double Data Rate (LPDDR2) SDRAM Standard,” 209-2F, June 2013. Specification (Rev2.0), ARM Inc. [4] DDR RAM by Gene Cooperman [5] “Mobile LPDDR2 SDRAM „by Micron technologies, 2010. Cndref is set Oprow =1 Cndref is set Activate O/P R/W is
  • 5. International Journal of Computer Applications Technology and Research Volume 3– Issue 6, 390 - 394, 2014 www.ijcat.com 394 [6] ”Verilog HDL, A Guide to Digital Design and Synthesis” by Samir Palnitkar, 2nd edition.