Functionality Guaranteed (No Good No Pay!), No NRE Payment (No Risk), Fastest cycle-time Minimum customer intervention (Fire & Forget) Any size FPGA

1. Automated FPGA to ASIC Conversion Experts

2. FPGA to ASIC, ASIC to ASIC, DSP to ASIC AUTOMATED CONVERSIONs

3. About Kaisemi is a fabless semiconductor vendor providing reduced-cost chip replacements KaiSemi is well established with FAB relationships KaiSemi relies on a strong and firm financial footing of Kai-Tek Group and a massive proven successful conversion experience. KaiSemi is focused on Automated conversion flow.

6. Power saving.

7. Secure fromcopy.

8. No Flash/EPROM Need .

9. NoPower-up Time.

10. EMI decreasing.

12. Netlist Conversion Concept Fast ASIC flow cycle No RTL touch: ensures Quality and Guarantee Automated Gate level No intervention needed by the customer

13. KaiSemi flow Traditional flow FPGARTL FPGA Netlist RTL fit to ASIC Functional Simulation Exclusive Workflow Full ASIC Synthesis KaiSemi in-house tools Timing + Functional Simulation DFT insertions ASIC Netlist Layout P&R Timing + Functional Simulation FAB hand-off

14. Full turnkey solution: From FPGA stage to Chip replacement production Automated Conversion with Full ASIC flow Well established infrastructure with FAB houses

15. Drop-in replacement: Fully compatible: Pin-to-Pin 2nd source or Functional compatible : reduced package

16. Exclusivity

17. Business model

18. Multi FPGAseripherals to an ASIC into a single-die replacement or into a multi-die single package replacement

19. End Of Life ASIC to ASIC Full Turnkey replacement without customer intervention Same business model of Functional Guarantee and “No NRE”

20. Summary Discussion Functionality Guaranteed (No Good No Pay!), because: No RTL touch ! Functional source code is untouched. Using ONLY the Netlist outcome of the proven working FPGA. Proven in-house semi-automated developed conversion tool with experience limits human errors No NRE Payment (No Risk), because: Our business model is targeted to ease on the customer. Based on minimum quantity ordering. Fastest cycle-time, because: Shortening ASIC flow cycle by using automated process and by starting, higher, from netlist stage Limiting the need for customers cycles of RTL flow, synthesis, verifications and back-annotations. Having well established coherent work flow with FABs. Minimum customer intervention (Fire & Forget), because: Customer is required to provide 2 main receivables: The FPGA netlist A verification test vectors. From that point on we proceed in posted mode, performing the whole ASIC process until providing a final working chip. Any size FPGA, because: KaiSemi conversion tool deals with any size and any type of FPGA with No limit on netlist size.