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Front–End Tools for Dynamic Reconfiguration in FPGA Devices 2005

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Kamil Kedzierski
Kamil Kedzierski

K. Kędzierski, J.M. Moreno, J. Cabestany, “Front–End Tools for Dynamic Reconfiguration in FPGA Devices”, Proceedings of the 12th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), June 2005, pages 121 – 126, Kraków, Poland

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Front-End Tools for Dynamic Reconfiguration in FPGA devices Kamil Kedzierski Technical University of Catalonia, Spain kkedzier@ac.upc.edu Kraków, 23.06.2005
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Project rationales and objectives • Different modes of reconfiguration: – Global, static – Partial, static – Partial, Dynamic: • • Reconfigure some areas of the FPGA while the rest of the design is still running Resulting challenge: Dynamic modules Static – Sequentially download the configuration of the dynamic blocks while maintaining, until the switch to the new configuration, the operation of the static blocks Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Project organization: Consortium: www.reconf.org • Geographical repartition over 6 European countries • 7 partners: 2 Academics, 1 Semiconductor Provider, 3 Users BELGIUM Deltatec CZECH REPUBLIC UTIA www.deltatec.be www.ideal-ist.cz FRANCE Atmel NTO ITALY Kayser Italia www.atmel.com MBDA France www.kayser.it www.mbda.net SPAIN GREECE Atmel Hellas UPC www-eel.upc.es/aha Kamil Kedzierski kkedzier@ac.upc.edu www.atmel.com - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Project organization WP1: Project Management WP3: Methodology • New Partitioning Methodology • Design Guidelines WP4: Front-end Tools design • • • • Constraints Editor Automatic Partitioning Tool VHDL Post-Processing Tool Configuration Controller Gen. WP5: Back-end Tools design • Modular Place & Route Tool • FPGA Re-configuration Tool Evaluation: Overall methodology • Mock up for evaluation • Medical Application Kamil Kedzierski kkedzier@ac.upc.edu WP6: Evaluation: States Machine • Mock up for evaluation • Control for Space Application WP7: Evaluation: Complex algorithms; Real time • Mock up for evaluation • Video Application WP8: Evaluation: Data management; Test & debug • Mock up for evaluation • Aeronautic Application - All disclosure and / or reproduction rights reserved - WP9: Dissemination & Implementation • Specifications of the D_FPGA Characteristics • Specifications of the Design Environment • Web page: www.reconf.org • Third Party for Front End Tools WP2: D_FPGA & Tools Specifications
FET for Dynamic Reconfiguration In FPGA Kraków 2005 The Design Flow KEY Inputs / Outputs. Only the main ones are indicated for clarity pupose Indication of the sequence between tasks (logical & temporal) Tasks specific to partial dynamic reconfiguration and requiring dedicated tools Link to the task that generated the outputs Tasks identical to the ones of the «classical design flow», using «standard» tools Updated constraints file Technical specifications Chip architecture Standard HDL files Chip modelling Scheduler C files HDL files Scheduler HDL files (static & dynamic) - Standard SW environment HW / SW co-simulation Bit stream files Standard HDL simulation Constraints definition Configuration controller generator Standard HDL synthesis Standard HDL simulation Partitioning Standard HDL simulation VHDL post-processing Front End Technology transparent Inputs from high level design tools: - Constraints file MatLab, Celoxica... Modular place & route D_FPGA reconfiguration tool Partial simulations Library creation Back End Technology dependent Instrumented HDL files Configuration Controller Generator Manual Partitioning Tool Kamil Kedzierski kkedzier@ac.upc.edu Temporal system planner - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Manual Partitioning Tool - Features • Reads VHDL source files • Hierarchical graphical representation of internal structure (input & output code), direct import of VHDL dynamic modules possible • Possibility for setting, editing and checking constraints for every dynamic module: – Conditions for loading / unloading dynamic modules • Time based (Clock cycle), Frame based (periodic), Signal event based (asynchronous) – Exclusive constraints between dynamic modules – Interface between application and configuration controller (status) – Bit stream organization in the storage memory • Generation of the interfaces between dynamic and static parts • Output contains source files for the dynamic modules, interfaces, static parts and DCF file Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Manual partitioning tool – User Interface Tree Browser Signal List Input Output Source Code Viewer Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 VHDL Post-Processing Tool - Features • Permits to carry out a functional validation for the results of the partitioning process – Verify if exclusive constraints are satisfied – Identify the active dynamic modules at any given time – Analyse the effect of unloaded dynamic modules on the whole design • Dynamic simulation process based on the DCS (Dynamic Circuit Switch) techniques proposed by Lysaght et al • Activation/Deactivation of dynamic modules emulated by means of isolation switches • Generates a functional description of the configuration controller (Schedule Control Module - SCM) and the isolation switches • Dynamic simulation fully compatible with static verification (same set of stimuli) Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA VHDL Post-Processing Tool, organisation of the simulation process SCM Dynamic Module 1 Dynamic Module 2 Static Module 1 Static Module 2 Dynamic Module N SCM control Isolation switch D_Module driver Static node X (D_Module being re-configured) Z (D_Module not present) Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved - Kraków 2005
FET for Dynamic Reconfiguration In FPGA VHDL Post-Processing Tool, organisation of the simulation process Kraków 2005 Dynamic Module 1 Static Module 2 Static Module 1 Dynamic Module 2 DM1 time DM2 ON REC OFF time Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA VHDL Post-Processing Tool, organisation of the simulation process Kraków 2005 Dynamic Module 1 Static Module 2 Static Module 1 Dynamic Module 2 DM1 time DM2 ON REC OFF time Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA VHDL Post-Processing Tool, organisation of the simulation process Kraków 2005 Dynamic Module 1 Static Module 2 Static Module 1 Dynamic Module 2 DM1 time DM2 ON REC OFF time Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Configuration Controller Generator (CCG), organization • CCG is a collection of two tools. Therefore, the following parts of the functionality may be distinguished: – VHDL-Post Processing Tool (Simulation Tool) generates: • Bidirectional switch, • Dynamic modules with added switches description • Functional Configuration Controller • Top-level file, • Model simulation *.do file – Configuration Controller Generator generates: • Physical Configuration Controller (in both VHDL and C code) Kamil Kedzierski kkedzier@ac.upc.edu • Reconf Interface, that is a collection of: – Event Detector – Sequential Scheduler – Physical Configuration Controller in VHDL code – Physical Interface - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Hardware Controller Verification process Stimuli Static part AI Reconf Interface IS TOP Entity Dynamic_Module_1 Reconfiguratio n Interface • AI: Application Interface • IS: Isolation switches IS IS Kamil Kedzierski kkedzier@ac.upc.edu Dynamic_Module_1 Dynamic_Module_1 - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Reconf Interface detailed view Application signals/ ports - event signals - clock signal - status signal Event Detector Switch control ports Reflects the conditions for loading or unloading the dynamic modules as specified in the DCF file relative to the design. Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Reconf Interface detailed view Application signals/ ports - event signals - clock signal - status signal Event Detector Sequential Scheduler Switch control ports Responsible for sequentially loading dynamic bit streams accordingly to the events detected by the event detector. Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Reconf Interface detailed view Application signals/ ports - event signals - clock signal - status signal Event Detector Sequential Scheduler Physical Configuration Controller Switch control ports Responsible for sequentially requesting all the bit stream data of the bit stream associated to the bit stream Id requested by the Sequential Scheduler. It is also responsible for reading the start and end pointers of the bit stream to load. Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Reconf Interface detailed view Application signals/ ports - event signals - clock signal - status signal Event Detector Sequential Scheduler Physical Configuration Controller Physical Interface Switch control ports Responsible for managing internal or external reconfiguration ports of the D_FPGA and internal/external bit stream memory. Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved - Reconf. port/ bit stream memory
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Reconf Interface detailed view Application signals/ ports - event signals - clock signal - status signal Event Detector Sequential Scheduler Physical Configuration Controller Physical Interface Reconf. port/ bit stream memory Switch control ports Device independent part Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved - Device dependent part
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Putting it all together: the Design Flow d_module_1 static P1 P2 P5 d_module_2 P3 P4 Kamil Kedzierski kkedzier@ac.upc.edu P6 - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Putting it all together: the Design Flow d_module_1 static P2 P1 P5 cut P ? d_module_2 P3 P6 P4 Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Putting it all together: the Design Flow (functional simulation) S static P1 d_module_1 P2 S P5 S cut P d_module_2 P3 S S S S event signals FCC switch control cut control Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved - P6 P4
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 Conclusions • Presented CAD environment allows the designer to proceed the dynamic reconfiguration in dynamically reconfigurable FPGA devices using currently available HDL tools • The user is fully supported during the whole process: starting from input static VHDL files until a final VHDL description of a dynamic behaviour of a design • Presented environment is a good candidate for the designer whenever the flexibility of tools and user convenience has to be high Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
FET for Dynamic Reconfiguration In FPGA Kraków 2005 About the Author • Currently working in High Performance Computing research group of the Computer Architecture Department at Universitat Politécnica de Catalunya, Barcelona (http://www.ac.upc.edu) • Topics: high performance processor architectures, runtime support for parallel programming models, and performance tuning applications for supercomputing • Last 5 years: more than 250 published papers in refereed international conferences, and 25 PhD thesis • Come join us! contact: kkedzier@ac.upc.edu Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -

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Front–End Tools for Dynamic Reconfiguration in FPGA Devices 2005

  • 1. Front-End Tools for Dynamic Reconfiguration in FPGA devices Kamil Kedzierski Technical University of Catalonia, Spain kkedzier@ac.upc.edu Kraków, 23.06.2005
  • 2. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 3. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Project rationales and objectives • Different modes of reconfiguration: – Global, static – Partial, static – Partial, Dynamic: • • Reconfigure some areas of the FPGA while the rest of the design is still running Resulting challenge: Dynamic modules Static – Sequentially download the configuration of the dynamic blocks while maintaining, until the switch to the new configuration, the operation of the static blocks Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 4. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Project organization: Consortium: www.reconf.org • Geographical repartition over 6 European countries • 7 partners: 2 Academics, 1 Semiconductor Provider, 3 Users BELGIUM Deltatec CZECH REPUBLIC UTIA www.deltatec.be www.ideal-ist.cz FRANCE Atmel NTO ITALY Kayser Italia www.atmel.com MBDA France www.kayser.it www.mbda.net SPAIN GREECE Atmel Hellas UPC www-eel.upc.es/aha Kamil Kedzierski kkedzier@ac.upc.edu www.atmel.com - All disclosure and / or reproduction rights reserved -
  • 5. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Project organization WP1: Project Management WP3: Methodology • New Partitioning Methodology • Design Guidelines WP4: Front-end Tools design • • • • Constraints Editor Automatic Partitioning Tool VHDL Post-Processing Tool Configuration Controller Gen. WP5: Back-end Tools design • Modular Place & Route Tool • FPGA Re-configuration Tool Evaluation: Overall methodology • Mock up for evaluation • Medical Application Kamil Kedzierski kkedzier@ac.upc.edu WP6: Evaluation: States Machine • Mock up for evaluation • Control for Space Application WP7: Evaluation: Complex algorithms; Real time • Mock up for evaluation • Video Application WP8: Evaluation: Data management; Test & debug • Mock up for evaluation • Aeronautic Application - All disclosure and / or reproduction rights reserved - WP9: Dissemination & Implementation • Specifications of the D_FPGA Characteristics • Specifications of the Design Environment • Web page: www.reconf.org • Third Party for Front End Tools WP2: D_FPGA & Tools Specifications
  • 6. FET for Dynamic Reconfiguration In FPGA Kraków 2005 The Design Flow KEY Inputs / Outputs. Only the main ones are indicated for clarity pupose Indication of the sequence between tasks (logical & temporal) Tasks specific to partial dynamic reconfiguration and requiring dedicated tools Link to the task that generated the outputs Tasks identical to the ones of the «classical design flow», using «standard» tools Updated constraints file Technical specifications Chip architecture Standard HDL files Chip modelling Scheduler C files HDL files Scheduler HDL files (static & dynamic) - Standard SW environment HW / SW co-simulation Bit stream files Standard HDL simulation Constraints definition Configuration controller generator Standard HDL synthesis Standard HDL simulation Partitioning Standard HDL simulation VHDL post-processing Front End Technology transparent Inputs from high level design tools: - Constraints file MatLab, Celoxica... Modular place & route D_FPGA reconfiguration tool Partial simulations Library creation Back End Technology dependent Instrumented HDL files Configuration Controller Generator Manual Partitioning Tool Kamil Kedzierski kkedzier@ac.upc.edu Temporal system planner - All disclosure and / or reproduction rights reserved -
  • 7. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 8. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Manual Partitioning Tool - Features • Reads VHDL source files • Hierarchical graphical representation of internal structure (input & output code), direct import of VHDL dynamic modules possible • Possibility for setting, editing and checking constraints for every dynamic module: – Conditions for loading / unloading dynamic modules • Time based (Clock cycle), Frame based (periodic), Signal event based (asynchronous) – Exclusive constraints between dynamic modules – Interface between application and configuration controller (status) – Bit stream organization in the storage memory • Generation of the interfaces between dynamic and static parts • Output contains source files for the dynamic modules, interfaces, static parts and DCF file Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 9. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Manual partitioning tool – User Interface Tree Browser Signal List Input Output Source Code Viewer Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 10. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 11. FET for Dynamic Reconfiguration In FPGA Kraków 2005 VHDL Post-Processing Tool - Features • Permits to carry out a functional validation for the results of the partitioning process – Verify if exclusive constraints are satisfied – Identify the active dynamic modules at any given time – Analyse the effect of unloaded dynamic modules on the whole design • Dynamic simulation process based on the DCS (Dynamic Circuit Switch) techniques proposed by Lysaght et al • Activation/Deactivation of dynamic modules emulated by means of isolation switches • Generates a functional description of the configuration controller (Schedule Control Module - SCM) and the isolation switches • Dynamic simulation fully compatible with static verification (same set of stimuli) Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 12. FET for Dynamic Reconfiguration In FPGA VHDL Post-Processing Tool, organisation of the simulation process SCM Dynamic Module 1 Dynamic Module 2 Static Module 1 Static Module 2 Dynamic Module N SCM control Isolation switch D_Module driver Static node X (D_Module being re-configured) Z (D_Module not present) Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved - Kraków 2005
  • 13. FET for Dynamic Reconfiguration In FPGA VHDL Post-Processing Tool, organisation of the simulation process Kraków 2005 Dynamic Module 1 Static Module 2 Static Module 1 Dynamic Module 2 DM1 time DM2 ON REC OFF time Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 14. FET for Dynamic Reconfiguration In FPGA VHDL Post-Processing Tool, organisation of the simulation process Kraków 2005 Dynamic Module 1 Static Module 2 Static Module 1 Dynamic Module 2 DM1 time DM2 ON REC OFF time Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 15. FET for Dynamic Reconfiguration In FPGA VHDL Post-Processing Tool, organisation of the simulation process Kraków 2005 Dynamic Module 1 Static Module 2 Static Module 1 Dynamic Module 2 DM1 time DM2 ON REC OFF time Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 16. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 17. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Configuration Controller Generator (CCG), organization • CCG is a collection of two tools. Therefore, the following parts of the functionality may be distinguished: – VHDL-Post Processing Tool (Simulation Tool) generates: • Bidirectional switch, • Dynamic modules with added switches description • Functional Configuration Controller • Top-level file, • Model simulation *.do file – Configuration Controller Generator generates: • Physical Configuration Controller (in both VHDL and C code) Kamil Kedzierski kkedzier@ac.upc.edu • Reconf Interface, that is a collection of: – Event Detector – Sequential Scheduler – Physical Configuration Controller in VHDL code – Physical Interface - All disclosure and / or reproduction rights reserved -
  • 18. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Hardware Controller Verification process Stimuli Static part AI Reconf Interface IS TOP Entity Dynamic_Module_1 Reconfiguratio n Interface • AI: Application Interface • IS: Isolation switches IS IS Kamil Kedzierski kkedzier@ac.upc.edu Dynamic_Module_1 Dynamic_Module_1 - All disclosure and / or reproduction rights reserved -
  • 19. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Reconf Interface detailed view Application signals/ ports - event signals - clock signal - status signal Event Detector Switch control ports Reflects the conditions for loading or unloading the dynamic modules as specified in the DCF file relative to the design. Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 20. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Reconf Interface detailed view Application signals/ ports - event signals - clock signal - status signal Event Detector Sequential Scheduler Switch control ports Responsible for sequentially loading dynamic bit streams accordingly to the events detected by the event detector. Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 21. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Reconf Interface detailed view Application signals/ ports - event signals - clock signal - status signal Event Detector Sequential Scheduler Physical Configuration Controller Switch control ports Responsible for sequentially requesting all the bit stream data of the bit stream associated to the bit stream Id requested by the Sequential Scheduler. It is also responsible for reading the start and end pointers of the bit stream to load. Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 22. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Reconf Interface detailed view Application signals/ ports - event signals - clock signal - status signal Event Detector Sequential Scheduler Physical Configuration Controller Physical Interface Switch control ports Responsible for managing internal or external reconfiguration ports of the D_FPGA and internal/external bit stream memory. Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved - Reconf. port/ bit stream memory
  • 23. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Reconf Interface detailed view Application signals/ ports - event signals - clock signal - status signal Event Detector Sequential Scheduler Physical Configuration Controller Physical Interface Reconf. port/ bit stream memory Switch control ports Device independent part Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved - Device dependent part
  • 24. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 25. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Putting it all together: the Design Flow d_module_1 static P1 P2 P5 d_module_2 P3 P4 Kamil Kedzierski kkedzier@ac.upc.edu P6 - All disclosure and / or reproduction rights reserved -
  • 26. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Putting it all together: the Design Flow d_module_1 static P2 P1 P5 cut P ? d_module_2 P3 P6 P4 Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 27. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Putting it all together: the Design Flow (functional simulation) S static P1 d_module_1 P2 S P5 S cut P d_module_2 P3 S S S S event signals FCC switch control cut control Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved - P6 P4
  • 28. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Outline • Introduction • Manual Partitioning Tool • VHDL-Post Processing Tool • Configuration Controller Generator • Putting it all together • Conclusions Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 29. FET for Dynamic Reconfiguration In FPGA Kraków 2005 Conclusions • Presented CAD environment allows the designer to proceed the dynamic reconfiguration in dynamically reconfigurable FPGA devices using currently available HDL tools • The user is fully supported during the whole process: starting from input static VHDL files until a final VHDL description of a dynamic behaviour of a design • Presented environment is a good candidate for the designer whenever the flexibility of tools and user convenience has to be high Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -
  • 30. FET for Dynamic Reconfiguration In FPGA Kraków 2005 About the Author • Currently working in High Performance Computing research group of the Computer Architecture Department at Universitat Politécnica de Catalunya, Barcelona (http://www.ac.upc.edu) • Topics: high performance processor architectures, runtime support for parallel programming models, and performance tuning applications for supercomputing • Last 5 years: more than 250 published papers in refereed international conferences, and 25 PhD thesis • Come join us! contact: kkedzier@ac.upc.edu Kamil Kedzierski kkedzier@ac.upc.edu - All disclosure and / or reproduction rights reserved -