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INTEGRATED CIRCUITS




  DATA SHEET
     For a complete data sheet, please also download:

     • The IC04 LOCMOS HE4000B Logic
       Family Specifications HEF, HEC
     • The IC04 LOCMOS HE4000B Logic
       Package Outlines/Information HEF, HEC




  HEF4518B
  MSI
  Dual BCD counter
Product specification                                January 1995
File under Integrated Circuits, IC04
Philips Semiconductors                                                                                Product specification

                                                                                                          HEF4518B
  Dual BCD counter
                                                                                                               MSI

DESCRIPTION                                                        LOW transition of the CP1 input if CP0 is LOW. Either CP0
                                                                   or CP1 may be used as the clock input to the counter and
T he HEF4518B is a dual 4-bit internally synchronous BCD
                                                                   the other clock input may be used as a clock enable input.
counter. The counter has an active HIGH clock input
                                                                   A HIGH on MR resets the counter (O0 to O3 = LOW)
(CP0) and an active LOW clock input (CP1), buffered
                                                                   independent of CP0, CP1.
outputs from all four bit positions (O0 to O3) and an active
                                                                   Schmitt-trigger action in the clock input makes the circuit
HIGH overriding asynchronous master reset input (MR).
                                                                   highly tolerant to slower clock rise and fall times.
The counter advances on either the LOW to HIGH
transition of the CP0 input if CP1 is HIGH or the HIGH to




                                                                                    Fig.2 Pinning diagram.




                                                                   HEF4518BP(N):        16-lead DIL; plastic (SOT38-1)
                                                                   HEF4518BD(F):        16-lead DIL; ceramic (cerdip) (SOT74)
                                                                   HEF4518BT(D):        16-lead SO; plastic (SOT109-1)
                                                                   ( ): Package Designator North America

                Fig.1 Functional diagram.



PINNING                                                            APPLICATION INFORMATION
CP0A, CP0B         clock inputs (L to H triggered)                 Some examples of applications for the HEF4518B are:
CP1A, CP1B         clock inputs (H to L triggered)                 • Multistage synchronous counting.
MRA, MRB           master reset inputs                             • Multistage asynchronous counting.
O0A to O3A         outputs                                         • Frequency dividers.
O0B to O3B         outputs
                                                                   FAMILY DATA, IDD LIMITS category MSI
                                                                   See Family Specifications




January 1995                                                   2
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January 1995




                                                                                                                                                                                           Philips Semiconductors
                                                                                                                                                                        Dual BCD counter
                                                                        Fig.3 Logic diagram (one counter).
3




               FUNCTION TABLE

                 CP0      CP1      MR            MODE
                            H       L     counter advances
                   L                L     counter advances
                            X       L     no change
                  X                 L     no change
                            L       L     no change
                  H                 L     no change
                  X         X       H     O0 to O3 = LOW

               Notes




                                                                                                                                                                                           Product specification
                                                                                                                                                                      HEF4518B
               1. H = HIGH state (the more positive voltage)
                  L = LOW state (the less positive voltage)
                  X = state is immaterial
                       = positive-going transition




                                                                                                                                                                           MSI
                       = negative-going transition
Philips Semiconductors                                                                          Product specification

                                                                                                 HEF4518B
  Dual BCD counter
                                                                                                      MSI

AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns

                              VDD                                                   TYPICAL EXTRAPOLATION
                                        SYMBOL       MIN. TYP.        MAX.
                               V                                                           FORMULA
Propagation delays
   CP0 , CP1 → On                 5                            120     240 ns      93 ns + (0,55 ns/pF) CL
      HIGH to LOW               10     tPHL                     55     110 ns      44 ns + (0,23 ns/pF) CL
                                15                              40      80 ns      32 ns + (0,16 ns/pF) CL
                                  5                            120     240 ns      93 ns + (0,55 ns/pF) CL
      LOW to HIGH               10     tPLH                     55     110 ns      44 ns + (0,23 ns/pF) CL
                                15                              40      80 ns      32 ns + (0,16 ns/pF) CL
   MR → On                        5                             75     150 ns      48 ns + (0,55 ns/pF) CL
      HIGH to LOW               10     tPHL                     35      70 ns      24 ns + (0,23 ns/pF) CL
                                15                              25      50 ns      17 ns + (0,16 ns/pF) CL
Output transition
   times                          5                            60      120 ns      10 ns + (1,0 ns/pF) CL
      HIGH to LOW               10     tTHL                     30      60 ns       9 ns + (0,42 ns/pF) CL
                                15                              20      40 ns       6 ns + (0,28 ns/pF) CL
                                  5                             60     120 ns      10 ns + (1,0 ns/pF) CL
      LOW to HIGH               10     tTLH                     30      60 ns       9 ns + (0,42 ns/pF) CL
                                15                              20      40 ns       6 ns + (0,28 ns/pF) CL
Minimum CP0                       5                 60          30           ns
   pulse width; LOW             10     tWCPL        30          15           ns
                                15                  20          10           ns
Minimum CP1                       5                 60          30           ns
   pulse width; HIGH            10     tWCPH        30          15           ns
                                15                  20          10           ns
Minimum MR                        5                 30          15           ns
   pulse width; HIGH            10     tWMRH        20          10           ns
                                15                  16           8           ns
Recovery time                     5                 50          25           ns
                                                                                      see also waveforms
   for MR                       10     tRMR         30          15           ns
                                                                                      Figs 4 and 5
                                15                  20          10           ns
Set-up times                      5                 50          25           ns
   CP0 → CP1                    10     tsu          30          15           ns
                                15                  20          10           ns
                                  5                 50          25           ns
   CP1 → CP0                    10     tsu          30          15           ns
                                15                  20          10           ns
Maximum clock                     5                 8           16           MHz
   pulse frequency              10     fmax         15          30           MHz
                                15                  20          40           MHz


January 1995                                               4
Philips Semiconductors                                                                        Product specification

                                                                                               HEF4518B
  Dual BCD counter
                                                                                                    MSI

AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns

                                VDD
                                           TYPICAL FORMULA FOR P (µW)
                                 V
Dynamic power                      5      750fi + ∑ (foCL) × VDD2            where
   dissipation per                10    3300 fi + ∑ (foCL) × VDD   2         fi = input freq. (MHz)
   package (P)                    15    8000 fi + ∑ (foCL) × VDD2            fo = output freq. (MHz)
                                                                             CL = load capacitance (pF)
                                                                             ∑ (foCL) = sum of outputs
                                                                             VDD = supply voltage (V)




               Fig.4 Waveforms showing recovery time for MR; minimum CP0, CP1 and MR pulse widths.




January 1995                                               5
Philips Semiconductors                                                                     Product specification

                                                                                             HEF4518B
  Dual BCD counter
                                                                                                  MSI




          Fig.5 Waveforms showing set-up times for CP0 to CP1 and CP1 to CP0, and propagation delays.




January 1995                                          6
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January 1995




                                                                                                                                                                                           Philips Semiconductors
                                                                                                                                                                        Dual BCD counter
                                                                              Fig.6 Timing diagram.
7




                                                                                                                                                                                           Product specification
                                                                                                                                                                      HEF4518B
                                                                                                                                                                           MSI
This datasheet has been download from:

      www.datasheetcatalog.com

Datasheets for electronics components.

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Hef4518 bd

  • 1. INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4518B MSI Dual BCD counter Product specification January 1995 File under Integrated Circuits, IC04
  • 2. Philips Semiconductors Product specification HEF4518B Dual BCD counter MSI DESCRIPTION LOW transition of the CP1 input if CP0 is LOW. Either CP0 or CP1 may be used as the clock input to the counter and T he HEF4518B is a dual 4-bit internally synchronous BCD the other clock input may be used as a clock enable input. counter. The counter has an active HIGH clock input A HIGH on MR resets the counter (O0 to O3 = LOW) (CP0) and an active LOW clock input (CP1), buffered independent of CP0, CP1. outputs from all four bit positions (O0 to O3) and an active Schmitt-trigger action in the clock input makes the circuit HIGH overriding asynchronous master reset input (MR). highly tolerant to slower clock rise and fall times. The counter advances on either the LOW to HIGH transition of the CP0 input if CP1 is HIGH or the HIGH to Fig.2 Pinning diagram. HEF4518BP(N): 16-lead DIL; plastic (SOT38-1) HEF4518BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4518BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.1 Functional diagram. PINNING APPLICATION INFORMATION CP0A, CP0B clock inputs (L to H triggered) Some examples of applications for the HEF4518B are: CP1A, CP1B clock inputs (H to L triggered) • Multistage synchronous counting. MRA, MRB master reset inputs • Multistage asynchronous counting. O0A to O3A outputs • Frequency dividers. O0B to O3B outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2
  • 3. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 Philips Semiconductors Dual BCD counter Fig.3 Logic diagram (one counter). 3 FUNCTION TABLE CP0 CP1 MR MODE H L counter advances L L counter advances X L no change X L no change L L no change H L no change X X H O0 to O3 = LOW Notes Product specification HEF4518B 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition MSI = negative-going transition
  • 4. Philips Semiconductors Product specification HEF4518B Dual BCD counter MSI AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD TYPICAL EXTRAPOLATION SYMBOL MIN. TYP. MAX. V FORMULA Propagation delays CP0 , CP1 → On 5 120 240 ns 93 ns + (0,55 ns/pF) CL HIGH to LOW 10 tPHL 55 110 ns 44 ns + (0,23 ns/pF) CL 15 40 80 ns 32 ns + (0,16 ns/pF) CL 5 120 240 ns 93 ns + (0,55 ns/pF) CL LOW to HIGH 10 tPLH 55 110 ns 44 ns + (0,23 ns/pF) CL 15 40 80 ns 32 ns + (0,16 ns/pF) CL MR → On 5 75 150 ns 48 ns + (0,55 ns/pF) CL HIGH to LOW 10 tPHL 35 70 ns 24 ns + (0,23 ns/pF) CL 15 25 50 ns 17 ns + (0,16 ns/pF) CL Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL Minimum CP0 5 60 30 ns pulse width; LOW 10 tWCPL 30 15 ns 15 20 10 ns Minimum CP1 5 60 30 ns pulse width; HIGH 10 tWCPH 30 15 ns 15 20 10 ns Minimum MR 5 30 15 ns pulse width; HIGH 10 tWMRH 20 10 ns 15 16 8 ns Recovery time 5 50 25 ns see also waveforms for MR 10 tRMR 30 15 ns Figs 4 and 5 15 20 10 ns Set-up times 5 50 25 ns CP0 → CP1 10 tsu 30 15 ns 15 20 10 ns 5 50 25 ns CP1 → CP0 10 tsu 30 15 ns 15 20 10 ns Maximum clock 5 8 16 MHz pulse frequency 10 fmax 15 30 MHz 15 20 40 MHz January 1995 4
  • 5. Philips Semiconductors Product specification HEF4518B Dual BCD counter MSI AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD TYPICAL FORMULA FOR P (µW) V Dynamic power 5 750fi + ∑ (foCL) × VDD2 where dissipation per 10 3300 fi + ∑ (foCL) × VDD 2 fi = input freq. (MHz) package (P) 15 8000 fi + ∑ (foCL) × VDD2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) Fig.4 Waveforms showing recovery time for MR; minimum CP0, CP1 and MR pulse widths. January 1995 5
  • 6. Philips Semiconductors Product specification HEF4518B Dual BCD counter MSI Fig.5 Waveforms showing set-up times for CP0 to CP1 and CP1 to CP0, and propagation delays. January 1995 6
  • 7. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 Philips Semiconductors Dual BCD counter Fig.6 Timing diagram. 7 Product specification HEF4518B MSI
  • 8. This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.