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1. Presented By Adam Corbin and Michael Hughes

2. Outline
 Introduction
 Energy-Aware Processors
 OS Energy Management
 Power Reduction through Architectural
Design
 Reducing Power through Circuitry
 Smart Batteries
 Tools and Packages for Low-Power
Design

3. Introduction
 Mobile devices have limited battery
power
 Remote areas to charge batteries
 Battery life is only expected to grow
10-20% over the next 10 years
 Software solutions
 Hardware solutions
 Batteries
 Circuitry

4. Energy-Aware Processors
 Dynamic Voltage/Frequency Scaling
(DVFS)
 Scheduling Algorithms
 Computational Offloading
 Mobile Wireless Ad-Hoc Networks (MANETs)

5. Dynamic Voltage/Frequency
Scaling
 One of the more popular power
management schemes
 Easy implementation
 Performance suffers
 Most effective when hardware is more than
adequate for the tasks being run
 In resource-constrained mobile computing
systems with slower processors there may not
be much room DVFS techniques to save
energy

6. Scheduling Algorithms
 Classic computer science problem
 Mobile devices add to the complexity when
battery energy utilization is considered
 Algorithms are tailored to the specific
needs of the device
 Energy saving vs. processing performance or a
combination of the two

7. Computational Offloading
 Resource-limited computing device defers
computation to a more capable device
 A solution for Mobile Wireless Ad-Hoc
Networks (MANETs)
 Distribute computational tasks amongst
devices
 Improvement in both energy saving and
processing performance

8. OS Energy Management
 Dynamic Software Management (DSM)
Frameworks
 Constrained Power Management (CPM)

9. Dynamic Software
Management Frameworks
 Goals
 Improve battery utilization
 Avoid competition for limited energy
resources from multiple applications
 Energy demand prediction
 Critical component of framework
 Uses energy models for prediction of
application energy demand

10. Constrained Power
Management (CPM)
 Goals
 Manage both system resources and power of
an entire platform
 Can optimize energy or performance
 Quality of Service (QoS)
 CPM collects QoS requirements from
applications and coordinates device drivers to
support requested QoS

11. Power Reduction through
Architectural Design
 Caches
 Typically 30-60% of total processor area
 20-50% of processor power consumption
 Filter Caches & On-demand Selective
Cache
 Speculative Activation
 On-chip Memory

12. Filter Caches & On-demand
Selective Cache
 Filter Caches
 Reduce dynamic and static power
consumption
 Shrink the size of L1 and L2 cache
 Significant decrease in performance
 On-demand Selective Cache
 Shuts down parts of the cache according to
demand
 Suffers from same decrease in peformance

13. Speculative Activation
 Attempt to make a prediction of where
the required data may be located
 If prediction is correct, latency and dynamic
power consumption become similar to direct-
mapped cache
 If prediction is incorrect, cache is accessed
twice and results in additional latency

14. On-chip Memory
 Minimize external data communication
 Eliminates external frame buffers
 No off-chip memory support allows for
high-quality processing at a minimal
power level

15. Reducing Power though Circuitry
 Near-Threshold Computing
 Razor-Thin Margins
 Smaller Transistors
 All-Digital Phase Locking
 Smart Converters
 Next-Generation Dynamic Ram
 SmartReflix power and performance

16. Near-Threshold Computing
 Lower voltage
 Pros: Energy consumption
 Cons: performance loss, memory and
logic failures
 Moore’s law
 Energy efficiency problem
 32nm chip example
 Solution to improve performance

17. Razor-Thin Margins
 Run processors at the threshold voltage
 Reasons why chips run at higher voltages
 Incorporate error detection
 Research from U. Of Michigan
 Arm Cortex –M3
○ 60% more energy efficient

18. Smaller Transistors
 2-D vs. 3-D Transistor

19. Smaller Transistors Cont.
 37% increase in
performance
 Moore’s law
 Lower voltage
 50% less power
 Less leakage

20. All-Digital Phase Locking
 Phase-locked loops
 Lock in and track input signal
 Pace car analogy
 Used for synchronize the processor and
the clock
 Converting from analog to digital saves
power

21. Smart Converters
 The analog to digital converts use a
switched capacitor
 Oregon State University
 Loop of inverters
 Chiao Tung University in Taiwan
 Separate signal in 2 stages
○ 1 simple processing
○ 2 fine tuning

22. Next Generation of Dynamic Ram
 Samsung and Hynix on DDR4 ram
 Drop voltage from 1.5V to 1.2V
 Includes better clocking
 Faster algorithms for encoding data
 End result
 Consume less energy
 Higher bandwidth

23. Smart Batteries
 Background Info
 Memory effect
○ Solution: lithium ion
 Advanced Power Management(APM)
 Mobile device uses information
 Polling for suspicious activity
 Avoid stalling of devices and wasted energy

24. SmartReflix power and performance
 Static Techniques
 Power-gating
 Dynamic Techniques
 Dynamic power switching
 Adaptive voltage scaling
 Dynamic voltage/frequency scaling

25. SimpleScalar (Tools)
 Tool set
 Simulator to compare two different
machines
 Extended to the Power Analyzer
 For the ARM platform
 Exam the performance/power trade-offs
 Extended to the Wattch Project
 Web app

26. PowerScope (Tools)
 Step 1. Gathers information based on
processes

27. PowerScope Cont
 Step 2. Of- Line Analysis

28. PowerScope Cont.
 Output

29. Conclusions